soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function

According to BKDGs for families 15h 60-6fh or newer and families 16h the
ACPI MMIO decode enable bit is the second LSB, not the first LSB.

Additionally create another enable function for older families where
the register and bit is different.

It does not seem to impact any current board, but may be crucial for
incoming C bootblock implementations when this bit will need to be set
very early. Most likely this bit is set by AGESA right now.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 6 insertions, 1 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 57d24db5b2..c441ab8f63 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -101,7 +101,12 @@
  */
 
 /* Enable the AcpiMmio range at 0xfed80000 */
-void enable_acpimmio_decode(void);
+
+/* For older discrete FCHs */
+void enable_acpimmio_decode_pm24(void);
+
+/* For newer integrated FCHs */
+void enable_acpimmio_decode_pm04(void);
 
 /* Access PM registers using IO cycles */
 uint8_t pm_io_read8(uint8_t reg);