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| author | Charles Marslett <charles.marslett@silverbackltd.com> | 2018-07-24 10:43:33 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-09-24 19:42:47 +0000 |
| commit | 8165583ed9234364824c41b7b74153aba36b60ce (patch) | |
| tree | a15d1628ae3fbcdacf27485161a4dbfdb8310441 /src/soc/amd/common/block/include/amdblocks/psp.h | |
| parent | dd9b1d1dd5e8418d1c86984b55bb9b535d5d8f64 (diff) | |
| download | coreboot-8165583ed9234364824c41b7b74153aba36b60ce.tar.xz | |
amd/common/psp: Remove use of PspBaseLib
Eliminate the references to PspBaseLib.c and PspBaseLib.h in
agesa_headers.h. Fix psp.c references to definitions in those files
by adding them to include/amdblocks/psp.h.
BUG=b:78514564
TEST=Build and boot grunt/ChromeOS and restore an image from the internet.
Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a
Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27619
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks/psp.h')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index f16bb44e47..6e1a1f0f05 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -21,6 +21,21 @@ #include <stdint.h> #include <compiler.h> +/* Extra, Special Purpose Registers in the PSP PCI Config Space */ + +/* PSP Mirror Features Capabilities and Control Register */ +#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */ +#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */ +#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */ + +#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */ +#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */ + +#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */ + +#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ +#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ + /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMM_INFO 0x02 |