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authorRaul E Rangel <rrangel@chromium.org>2020-05-06 11:47:04 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 20:12:17 +0000
commit3f3f53cd5e05eead7a8b8616244a4665bd14b22b (patch)
tree3181c1d34ad472611ea5eccbceba198ed6b70618 /src/soc/amd/common/block/lpc/lpc_util.c
parent5819eab5a660f915e0d18dd7d948d2af2a231aa0 (diff)
downloadcoreboot-3f3f53cd5e05eead7a8b8616244a4665bd14b22b.tar.xz
util/sconfig: Add LPC and ESPI buses
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/lpc/lpc_util.c')
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