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| author | Nick Vaccaro <nvaccaro@google.com> | 2018-06-18 21:56:25 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 09:41:29 +0000 |
| commit | de31587a3a4834c18eab49aa7fd979a01f1fd3d1 (patch) | |
| tree | e57eec7a539b727771f4b7e3a18b63f2ec859aee /src/soc/amd/common/block/pi | |
| parent | 97bdb9aa31ada2b4fbf0aa5e0e3744294427f927 (diff) | |
| download | coreboot-de31587a3a4834c18eab49aa7fd979a01f1fd3d1.tar.xz | |
mb/google/poppy/variants/nocturne: disable p-states
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common/block/pi')
0 files changed, 0 insertions, 0 deletions