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author | Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> | 2020-03-05 11:44:24 -0700 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-13 12:39:12 +0000 |
commit | d6b7236732d8cc74545849f4b81af1d33e8758e2 (patch) | |
tree | 8203c3ad9d18a49d4bc243e0bdbe02b0fad77be0 /src/soc/amd/common/block/psp/psp_def.h | |
parent | a67c753d554c730c794726b1b65d07c9c383e264 (diff) | |
download | coreboot-d6b7236732d8cc74545849f4b81af1d33e8758e2.tar.xz |
soc/amd/common/psp: Split mailbox support into v1 and v2
Family 17h redefines the PSP command and status, and therefore the
steps required to send commands via the mailbox. Convert the existing
version into a v1 and add a v2. New Kconfig options allow the soc to
choose v1 vs. v2.
The v2 PSP begins responding to the mailbox command when the full
bit range is written. Define the new mailbox as a union of a u32
and a structure.
Additional PSP details may be found in the NDA publication (#55758)
AMD Platform Security Processor BIOS Architecture Design Guide for
AMD Family 17h Processors
Change the existing two soc functions that return pointers to void
pointers.
BUG=b:153677737
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d358fdae07da471640856f57568059e9487f6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/psp/psp_def.h')
-rw-r--r-- | src/soc/amd/common/block/psp/psp_def.h | 36 |
1 files changed, 29 insertions, 7 deletions
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 4b3ca6a352..37755166f0 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -5,6 +5,7 @@ #define __AMD_PSP_DEF_H__ #include <types.h> +#include <commonlib/helpers.h> /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 @@ -20,24 +21,42 @@ #define MBOX_BIOS_CMD_SMU_FW2 0x1a #define MBOX_BIOS_CMD_ABORT 0xfe -/* generic PSP interface status */ -#define STATUS_INITIALIZED 0x1 -#define STATUS_ERROR 0x2 -#define STATUS_TERMINATED 0x4 -#define STATUS_HALT 0x8 -#define STATUS_RECOVERY 0x10 +/* generic PSP interface status, v1 */ +#define PSPV1_STATUS_INITIALIZED BIT(0) +#define PSPV1_STATUS_ERROR BIT(1) +#define PSPV1_STATUS_TERMINATED BIT(2) +#define PSPV1_STATUS_HALT BIT(3) +#define PSPV1_STATUS_RECOVERY BIT(4) + +/* generic PSP interface status, v2 */ +#define PSPV2_STATUS_ERROR BIT(30) +#define PSPV2_STATUS_RECOVERY BIT(31) /* psp_mbox consists of hardware registers beginning at PSPx000070 * mbox_command: BIOS->PSP command, cleared by PSP when complete * mbox_status: BIOS->PSP interface status * cmd_response: pointer to command/response buffer */ -struct psp_mbox { +struct pspv1_mbox { u32 mbox_command; u32 mbox_status; u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ } __packed; +struct pspv2_mbox { + union { + u32 val; + struct pspv2_mbox_cmd_fields { + u16 mbox_status; + u8 mbox_command; + u32 reserved:6; + u32 recovery:1; + u32 ready:1; + } __packed fields; + }; + u64 cmd_response; +} __packed; + /* command/response format, BIOS builds this in memory * mbox_buffer_header: generic header * mbox_buffer: command-specific buffer format @@ -70,4 +89,7 @@ struct mbox_cmd_sx_info_buffer { #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ +/* This command needs to be implemented by the generation specific code. */ +int send_psp_command(u32 command, void *buffer); + #endif /* __AMD_PSP_DEF_H__ */ |