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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-11 02:43:07 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-12 20:49:10 +0000 |
| commit | 34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898 (patch) | |
| tree | 972a40dc74d75f5c99d628ff62c2422e352e9caf /src/soc/amd/common/block/smbus | |
| parent | 1b33205909c5a8f775eefd19107406a620a7fcc5 (diff) | |
| download | coreboot-34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898.tar.xz | |
soc/amd: add and use fch_enable_hpet_decode
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.
TEST=HPET still works on Mandolin.
Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/smbus')
| -rw-r--r-- | src/soc/amd/common/block/smbus/sm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 0b219e006d..b1b3db6192 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -13,6 +13,7 @@ static void sm_init(struct device *dev) { fch_enable_ioapic_decode(); setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + fch_configure_hpet(); } static u32 get_sm_mmio(struct device *dev) |