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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 18:18:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-02 21:27:03 +0000 |
| commit | 6443ad4a53ab65a2a9c1d29f422644e450c04cd7 (patch) | |
| tree | 4843082fa04ab74fd08b53aa01eb65165e8edb4f /src/soc/amd/common/block | |
| parent | 5b3831c75abe5fc50739984eaa70fbada2575bb7 (diff) | |
| download | coreboot-6443ad4a53ab65a2a9c1d29f422644e450c04cd7.tar.xz | |
soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block')
| -rw-r--r-- | src/soc/amd/common/block/aoac/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/aoac/Makefile.inc | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/aoac/aoac.c | 32 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/aoac.h | 4 |
4 files changed, 50 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/aoac/Kconfig b/src/soc/amd/common/block/aoac/Kconfig new file mode 100644 index 0000000000..361a46e035 --- /dev/null +++ b/src/soc/amd/common/block/aoac/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_AOAC + bool + default n + help + Select this option to add the common functions for the AOAC block to + the build. diff --git a/src/soc/amd/common/block/aoac/Makefile.inc b/src/soc/amd/common/block/aoac/Makefile.inc new file mode 100644 index 0000000000..4debc55928 --- /dev/null +++ b/src/soc/amd/common/block/aoac/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_AOAC),y) + +bootblock-y += aoac.c +romstage-y += aoac.c +verstage-y += aoac.c +ramstage-y += aoac.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c new file mode 100644 index 0000000000..c5f161bfcb --- /dev/null +++ b/src/soc/amd/common/block/aoac/aoac.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> + +/* This initiates the power on sequence, but doesn't wait for the device to be powered on. */ +void power_on_aoac_device(unsigned int dev) +{ + uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); + byte |= FCH_AOAC_PWR_ON_DEV; + byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; + byte |= FCH_AOAC_D0_INITIALIZED; + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); +} + +void power_off_aoac_device(unsigned int dev) +{ + uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); + byte &= ~FCH_AOAC_PWR_ON_DEV; + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); +} + +bool is_aoac_device_enabled(unsigned int dev) +{ + uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); + byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); + if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) + return true; + else + return false; +} diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index f4f58e66e0..ff5d0db169 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -32,4 +32,8 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) +bool is_aoac_device_enabled(unsigned int dev); +void power_on_aoac_device(unsigned int dev); +void power_off_aoac_device(unsigned int dev); + #endif /* AMD_BLOCK_AOAC_H */ |