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authorFurquan Shaikh <furquan@google.com>2020-05-09 17:18:48 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-12 18:59:38 +0000
commitd82c7d24ffc64e7caeaff6ccd7c79d3946142afc (patch)
tree190304f658c214a0ed963df02e95f690d1b485f7 /src/soc/amd/common
parent2f5183c7af57bdefc88999bba62896bbcfe606c6 (diff)
downloadcoreboot-d82c7d24ffc64e7caeaff6ccd7c79d3946142afc.tar.xz
soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions
This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/lpc.h11
-rw-r--r--src/soc/amd/common/block/lpc/lpc_util.c18
2 files changed, 24 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index d7a455a681..00210a7fe1 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -179,6 +179,15 @@ int lpc_find_wideio_range(uint16_t start, uint16_t size);
int lpc_set_wideio_range(uint16_t start, uint16_t size);
uintptr_t lpc_get_spibase(void);
-void lpc_set_spibase(uint32_t base, uint32_t enable);
+
+/*
+ * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform).
+ *
+ * eSPI base = SPI base + 0x10000
+ */
+void lpc_set_spibase(uint32_t base);
+
+/* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */
+void lpc_enable_spi_rom(uint32_t enable);
#endif /* __AMDBLOCKS_LPC_H__ */
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 97ef17c612..c9786e7aa2 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -322,19 +322,29 @@ uintptr_t lpc_get_spibase(void)
return (uintptr_t)base;
}
-void lpc_set_spibase(u32 base, u32 enable)
+void lpc_set_spibase(uint32_t base)
{
- u32 reg32;
+ uint32_t reg32;
+
+ reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
+
+ reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
+ reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
+
+ pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
+}
+
+void lpc_enable_spi_rom(uint32_t enable)
+{
+ uint32_t reg32;
/* only two types of CS# enables are allowed */
enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;
reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
- reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
reg32 |= enable;
- reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
}