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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-12 23:44:14 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 00:00:27 +0000 |
| commit | 0d2c0019e284aea3b1889579782495afb6e52daf (patch) | |
| tree | ac8a6a574b8f4be3f8264b5d3e2466b27eddc249 /src/soc/amd/common | |
| parent | 651d5214d25641052a757e3f6eec75e4a1af9f9c (diff) | |
| download | coreboot-0d2c0019e284aea3b1889579782495afb6e52daf.tar.xz | |
soc/amd/picasso/romstage: factor out chipset state saving functionality
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/pmlib.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pm/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pm/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pm/chipset_state.c | 27 |
4 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/pmlib.h b/src/soc/amd/common/block/include/amdblocks/pmlib.h index c778664a49..d9b80a29d1 100644 --- a/src/soc/amd/common/block/include/amdblocks/pmlib.h +++ b/src/soc/amd/common/block/include/amdblocks/pmlib.h @@ -17,4 +17,7 @@ enum { */ void pm_set_power_failure_state(void); +/* stash ACPI PM/GPE and GPIO wake state before FSP-M call */ +void fill_chipset_state(void); + #endif /* SOC_AMD_COMMON_BLOCK_PMLIB_H */ diff --git a/src/soc/amd/common/block/pm/Kconfig b/src/soc/amd/common/block/pm/Kconfig index c976d017ec..e250bf0a2b 100644 --- a/src/soc/amd/common/block/pm/Kconfig +++ b/src/soc/amd/common/block/pm/Kconfig @@ -10,4 +10,10 @@ if SOC_AMD_COMMON_BLOCK_PM config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y +config SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE + bool + help + Add common functionality to write CBMEM_ID_POWER_STATE for AMD + platforms that use FSP for hardware initialization. + endif # SOC_AMD_COMMON_BLOCK_PM diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc index f465e99ec1..f016a9db02 100644 --- a/src/soc/amd/common/block/pm/Makefile.inc +++ b/src/soc/amd/common/block/pm/Makefile.inc @@ -1 +1,3 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c + +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c new file mode 100644 index 0000000000..3a4a0ba506 --- /dev/null +++ b/src/soc/amd/common/block/pm/chipset_state.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpi.h> +#include <amdblocks/gpio_banks.h> +#include <amdblocks/pmlib.h> +#include <cbmem.h> +#include <string.h> + +static struct chipset_power_state chipset_state; + +void fill_chipset_state(void) +{ + acpi_fill_pm_gpe_state(&chipset_state.gpe_state); + gpio_fill_wake_state(&chipset_state.gpio_state); +} + +static void add_chipset_state_cbmem(int unused) +{ + struct chipset_power_state *state; + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + + if (state) + memcpy(state, &chipset_state, sizeof(*state)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem); |