diff options
author | Raul E Rangel <rrangel@chromium.org> | 2018-04-11 10:58:14 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-04-11 17:21:16 +0000 |
commit | 1f54e9571ed9588ce91ad8f3ef8a7f2481f88397 (patch) | |
tree | 519891c350e97ea0c4df146205896499c3f0478c /src/soc/amd/common | |
parent | d67a4bd5a7f2270294a83a15ba4bc58d16e67180 (diff) | |
download | coreboot-1f54e9571ed9588ce91ad8f3ef8a7f2481f88397.tar.xz |
soc/amd: Fix generating SMBIOS Type 17
The converter was setting SMBIOS values when dimm_info expects SPD
values.
dmidecode now shows the following:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 933 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 933 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Example debug output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): ' 00000000'
PartNumber(20): 'HMAA51S6AMR6N-UH '
CBMEM_ID_MEMINFO:
dimm_size: 8192
ddr_type: 0x1a
ddr_frequency: 933
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x4
bus_width: 3
serial: 0x00000000
module_part_number(18): 'HMAA51S6AMR6N-UH '
The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.
`mosys memory spd print all` is still failing though. I will look into
that next.
BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above
Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r-- | src/soc/amd/common/block/pi/amd_late_init.c | 44 |
1 files changed, 33 insertions, 11 deletions
diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 48c171806a..b0064a2f40 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -15,17 +15,22 @@ #include <arch/acpi.h> #include <bootstate.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <dimm_info_util.h> #include <memory_info.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> -static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, struct dimm_info *dimm) +/** + * Populate dimm_info using AGESA TYPE17_DMI_INFO. + */ +static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, + struct dimm_info *dimm) { size_t len, destlen; uint32_t offset; @@ -41,16 +46,34 @@ static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, struct dimm_info *dimm) offset = 0; strncpy((char *)dimm->serial, &dmi17->SerialNumber[offset], len); - dimm->dimm_size = dmi17->ExtSize; + + dimm->dimm_size = + smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize); + dimm->ddr_type = dmi17->MemoryType; - dimm->ddr_frequency = dmi17->Speed; + + /* + * dimm_info uses ddr_frequency for setting both config speed and max + * speed. Lets use config speed so we don't get the false impression + * that the RAM is running faster than it actually is. + */ + dimm->ddr_frequency = dmi17->ConfigSpeed; + dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = dmi17->MemoryType; - dimm->bus_width = dmi17->DataWidth; + + dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); + + dimm->bus_width = + smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->mod_id = dmi17->ManufacturerIdCode; + dimm->bank_locator = 0; + strncpy((char *)dimm->module_part_number, dmi17->PartNumber, - sizeof(dimm->module_part_number)); + sizeof(dimm->module_part_number)); + + dimm->module_part_number[sizeof(dimm->module_part_number) - 1] = 0; } static void print_dimm_info(const struct dimm_info *dimm) @@ -160,8 +183,7 @@ static void prepare_dmi_17(void *unused) mem_info->dimm_cnt = dimm_cnt; } -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - prepare_dmi_17, NULL); +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, prepare_dmi_17, NULL); static void agesawrapper_post_device(void *unused) { @@ -176,5 +198,5 @@ static void agesawrapper_post_device(void *unused) do_agesawrapper(agesawrapper_amdinitrtb, "amdinitrtb"); } -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, + NULL); |