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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-10 20:42:20 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-11 19:10:54 +0000 |
| commit | 316d59c1aa48aef4bf4c3ebd98db0b1255c666fa (patch) | |
| tree | 460ccede57b66ca6cf0c656cef464859b6086277 /src/soc/amd/common | |
| parent | c0d4eeb387f9892ad33e117ab3fc3648918e823a (diff) | |
| download | coreboot-316d59c1aa48aef4bf4c3ebd98db0b1255c666fa.tar.xz | |
soc/amd/common/espi_util: espi_send_command: improve error message
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.
Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 4415615545..b09d61d06a 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -470,7 +470,8 @@ static int espi_send_command(const struct espi_cmd *cmd) } if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { - espi_show_failure(cmd, "Error: eSPI status register bits set", status); + espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", + status); return -1; } |