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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-12-18 14:02:23 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-03 04:16:32 +0000
commit2469a9eee83df47916d44b9be7403a7eeb49f3ab (patch)
treee4916fa5f82cd38a15c4693475352f227cce0354 /src/soc/amd/common
parentbc17b6f98f50a9c295d59290328f439b49defc8d (diff)
downloadcoreboot-2469a9eee83df47916d44b9be7403a7eeb49f3ab.tar.xz
amdblocks/acpimmio: add missing MMIO functions
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h155
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio_map.h1
2 files changed, 156 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 46d088f0cb..b4a4b50a29 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -206,6 +206,36 @@ static inline void pm_write32(uint8_t reg, uint32_t value)
write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
+static inline uint8_t pm2_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_PMIO2_BASE + reg));
+}
+
+static inline uint16_t pm2_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_PMIO2_BASE + reg));
+}
+
+static inline uint32_t pm2_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_PMIO2_BASE + reg));
+}
+
+static inline void pm2_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+}
+
+static inline void pm2_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+}
+
+static inline void pm2_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+}
+
static inline uint8_t acpi_read8(uint8_t reg)
{
return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
@@ -336,6 +366,131 @@ static inline void misc_write32(uint8_t reg, uint32_t value)
write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
}
+/* Old GPIO configuration registers */
+static inline uint8_t gpio_100_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+}
+
+static inline uint16_t gpio_100_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+}
+
+static inline uint32_t gpio_100_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+}
+
+static inline void gpio_100_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+}
+
+static inline void gpio_100_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+}
+
+static inline void gpio_100_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+}
+
+/* New GPIO banks configuration registers */
+/* GPIO bank 0 */
+static inline uint8_t gpio0_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_GPIO0_BASE + reg));
+}
+
+static inline uint16_t gpio0_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_GPIO0_BASE + reg));
+}
+
+static inline uint32_t gpio0_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_GPIO0_BASE + reg));
+}
+
+static inline void gpio0_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+}
+
+static inline void gpio0_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+}
+
+static inline void gpio0_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+}
+
+/* GPIO bank 1 */
+static inline uint8_t gpio1_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_GPIO1_BASE + reg));
+}
+
+static inline uint16_t gpio1_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_GPIO1_BASE + reg));
+}
+
+static inline uint32_t gpio1_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_GPIO1_BASE + reg));
+}
+
+static inline void gpio1_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+}
+
+static inline void gpio1_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+}
+
+static inline void gpio1_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+}
+
+/* GPIO bank 2 */
+static inline uint8_t gpio2_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_GPIO2_BASE + reg));
+}
+
+static inline uint16_t gpio2_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_GPIO2_BASE + reg));
+}
+
+static inline uint32_t gpio2_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_GPIO2_BASE + reg));
+}
+
+static inline void gpio2_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+}
+
+static inline void gpio2_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+}
+
+static inline void gpio2_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+}
+
static inline uint8_t xhci_pm_read8(uint8_t reg)
{
return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
index 9a1584004b..4d62b39080 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -48,6 +48,7 @@
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
#define ACPIMMIO_SM_PCI_BASE 0xfed80000
+#define ACPIMMIO_GPIO_BASE_100 0xfed80100
#define ACPIMMIO_SMI_BASE 0xfed80200
#define ACPIMMIO_PMIO_BASE 0xfed80300
#define ACPIMMIO_PMIO2_BASE 0xfed80400