soc/amd/stoneyridge: Relocate MMIO access of ACPI registers

The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models.  Move the support from
soc//stoneyridge to soc//common.

BUG=b:131682806

Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 192 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc
index 1320849fc3..708631a5e9 100644
--- a/src/soc/amd/common/block/acpi/Makefile.inc
+++ b/src/soc/amd/common/block/acpi/Makefile.inc
@@ -1,2 +1,6 @@
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
+verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
 smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c
diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c
index 200b3c12f5..39e03e2c0c 100644
--- a/src/soc/amd/common/block/acpi/acpi.c
+++ b/src/soc/amd/common/block/acpi/acpi.c
@@ -14,9 +14,14 @@
  */
 
 #include <arch/acpi.h>
+#include <cbmem.h>
+#include <elog.h>
+#include <console/console.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpi.h>
 #include <halt.h>
+#include <security/vboot/vboot_common.h>
 
 void poweroff(void)
 {
@@ -31,3 +36,142 @@ void poweroff(void)
 	if (!ENV_SMM)
 		halt();
 }
+
+static uint16_t reset_pm1_status(void)
+{
+	uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS);
+	acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts);
+	return pm1_sts;
+}
+
+static void print_num_status_bits(int num_bits, uint32_t status,
+				  const char *const bit_names[])
+{
+	int i;
+
+	if (!status)
+		return;
+
+	for (i = num_bits - 1; i >= 0; i--) {
+		if (status & (1 << i)) {
+			if (bit_names[i])
+				printk(BIOS_DEBUG, "%s ", bit_names[i]);
+			else
+				printk(BIOS_DEBUG, "BIT%d ", i);
+		}
+	}
+}
+
+static uint16_t print_pm1_status(uint16_t pm1_sts)
+{
+	static const char *const pm1_sts_bits[16] = {
+		[0] = "TMROF",
+		[4] = "BMSTATUS",
+		[5] = "GBL",
+		[8] = "PWRBTN",
+		[10] = "RTC",
+		[14] = "PCIEXPWAK",
+		[15] = "WAK",
+	};
+
+	if (!pm1_sts)
+		return 0;
+
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
+	printk(BIOS_DEBUG, "\n");
+
+	return pm1_sts;
+}
+
+static void log_pm1_status(uint16_t pm1_sts)
+{
+	if (!CONFIG(ELOG))
+		return;
+
+	if (pm1_sts & WAK_STS)
+		elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
+				    acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
+
+	if (pm1_sts & PWRBTN_STS)
+		elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
+
+	if (pm1_sts & RTC_STS)
+		elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
+
+	if (pm1_sts & PCIEXPWAK_STS)
+		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+}
+
+static void save_sws(uint16_t pm1_status)
+{
+	struct soc_power_reg *sws;
+	uint32_t reg32;
+	uint16_t reg16;
+
+	sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg));
+	if (sws == NULL)
+		return;
+	sws->pm1_sts = pm1_status;
+	sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN);
+	reg32 = acpi_read32(MMIO_ACPI_GPE0_STS);
+	acpi_write32(MMIO_ACPI_GPE0_STS, reg32);
+	sws->gpe0_sts = reg32;
+	sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN);
+	reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
+	reg16 &= SLP_TYP;
+	sws->wake_from = reg16 >> SLP_TYP_SHIFT;
+}
+
+void acpi_clear_pm1_status(void)
+{
+	uint16_t pm1_sts = reset_pm1_status();
+
+	save_sws(pm1_sts);
+	log_pm1_status(pm1_sts);
+	print_pm1_status(pm1_sts);
+}
+
+int vboot_platform_is_resuming(void)
+{
+	if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS))
+		return 0;
+
+	uint16_t pm_cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
+	return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3;
+}
+
+/* If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume. */
+void set_pm1cnt_s5(void)
+{
+	uint16_t pm1;
+
+	pm1 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
+	pm1 &= ~SLP_TYP;
+	pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT;
+	acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1);
+}
+
+void vboot_platform_prepare_reboot(void)
+{
+	set_pm1cnt_s5();
+}
+
+void acpi_enable_sci(void)
+{
+	uint32_t pm1;
+
+	pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK);
+	pm1 |= ACPI_PM1_CNT_SCIEN;
+	acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1);
+}
+
+void acpi_disable_sci(void)
+{
+	uint32_t pm1;
+
+	pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK);
+	pm1 &= ~ACPI_PM1_CNT_SCIEN;
+	acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h
new file mode 100644
index 0000000000..cf266ed7d8
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/acpi.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_ACPI_H__
+#define __AMDBLOCKS_ACPI_H__
+
+#include <stdint.h>
+
+/* ACPI MMIO registers 0xfed80800 */
+#define MMIO_ACPI_PM1_STS		0x00
+#define MMIO_ACPI_PM1_EN		0x02
+#define MMIO_ACPI_PM1_CNT_BLK		0x04
+	  /* sleep types defined in arch/x86/include/arch/acpi.h */
+#define   ACPI_PM1_CNT_SCIEN		BIT(0)
+#define MMIO_ACPI_PM_TMR_BLK		0x08
+#define MMIO_ACPI_CPU_CONTROL		0x0c
+#define MMIO_ACPI_GPE0_STS		0x14
+#define MMIO_ACPI_GPE0_EN		0x18
+
+void acpi_clear_pm1_status(void);
+
+/*
+ * If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume.
+ */
+void set_pm1cnt_s5(void);
+void acpi_enable_sci(void);
+void acpi_disable_sci(void);
+
+#endif /* __AMDBLOCKS_ACPI_H__ */
diff --git a/src/soc/amd/common/block/s3/Kconfig b/src/soc/amd/common/block/s3/Kconfig
index 0880163d54..ebc1695d9b 100644
--- a/src/soc/amd/common/block/s3/Kconfig
+++ b/src/soc/amd/common/block/s3/Kconfig
@@ -1,6 +1,7 @@
 config SOC_AMD_COMMON_BLOCK_S3
 	bool
 	default n
+	depends on SOC_AMD_COMMON_BLOCK_ACPI
 	select CACHE_MRC_SETTINGS
 	select MRC_WRITE_NV_LATE
 	help
diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c
index 0ba2f13b46..74aa79c398 100644
--- a/src/soc/amd/common/block/s3/s3_resume.c
+++ b/src/soc/amd/common/block/s3/s3_resume.c
@@ -21,6 +21,7 @@
 #include <console/console.h>
 #include <soc/southbridge.h>
 #include <amdblocks/s3_resume.h>
+#include <amdblocks/acpi.h>
 
 /* Training data versioning is not supported or tracked. */
 #define DEFAULT_MRC_VERSION 0