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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 21:36:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 00:43:16 +0000 |
| commit | 6f8f9c969be9d471464f1b6a42b4bb1c2590db5c (patch) | |
| tree | 87dcfda6643117932f9f926e3f17d44e41fa1ec4 /src/soc/amd/picasso/Kconfig | |
| parent | 0dfaf33a1331ede41c052be20217abcf2b70e141 (diff) | |
| download | coreboot-6f8f9c969be9d471464f1b6a42b4bb1c2590db5c.tar.xz | |
soc/amd/picasso: move UART Kconfig options to common folder
The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 48 |
1 files changed, 1 insertions, 47 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c4c7baeaeb..e9930e9998 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -273,53 +274,6 @@ config PICASSO_ACPI_IO_BASE help Base address for the ACPI registers. -config AMD_SOC_CONSOLE_UART - bool "Use Picasso UART controller for console" - default n - select DRIVERS_UART_8250MEM - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - select UART_OVERRIDE_REFCLK - help - There are four memory-mapped UARTs controllers in Picasso at: - 0: 0xfedc9000 - 1: 0xfedca000 - 2: 0xfedc3000 - 3: 0xfedcf000 - -choice - prompt "UART Frequency" - depends on AMD_SOC_CONSOLE_UART - default AMD_SOC_UART_48MZ - -config AMD_SOC_UART_48MZ - bool "48 MHz clock" - help - Select this option for the most compatibility. - -config AMD_SOC_UART_1_8MZ - bool "1.8432 MHz clock" - help - Select this option if an old payload or Linux ttyS0 arguments - require it. - -endchoice - -config AMD_SOC_UART_LEGACY - bool "Decode legacy I/O range" - help - Assign I/O 3F8, 2F8, etc. to a Picasso UART. A UART accessed with I/O - does not allow all the features of MMIO. The MMIO decode is still - present when this option is used. - -config CONSOLE_UART_BASE_ADDRESS - depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART - hex - default 0xfedc9000 if UART_FOR_CONSOLE = 0 - default 0xfedca000 if UART_FOR_CONSOLE = 1 - default 0xfedc3000 if UART_FOR_CONSOLE = 2 - default 0xfedcf000 if UART_FOR_CONSOLE = 3 - config SMM_TSEG_SIZE hex default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |