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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-01-20 23:05:31 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-01 23:27:26 +0000 |
| commit | 00a220877c8fc27f161017e68b67fce23117c0ad (patch) | |
| tree | 27061b4324f4d79e650fb03e7674046409ca3ef6 /src/soc/amd/picasso/Kconfig | |
| parent | e04c2c4527d07583201003aa95f1ebc596c11e00 (diff) | |
| download | coreboot-00a220877c8fc27f161017e68b67fce23117c0ad.tar.xz | |
soc/amd/picasso: Add FSP support for including AGESA
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments. Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.
AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.
* Add fsp_memory_init() to romstage.c. Although Picasso comes out
of reset with DRAM alive, this call is added to maximize
compatibility and facilitate internal development. Future work
may look at removing it. AGESA reports the memory map to coreboot
via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
passed from AGESA. Note that relying on the TOM register happens
to be misleading when UMA is below 4GB.
BUG=b:147042464
TEST=Boot trembyle to payload
Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5996cc632e..c807ad4c7d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -47,6 +47,10 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SSE2 select RTC + select PLATFORM_USES_FSP2_0 + select FSP_USES_CB_STACK + select UDK_2017_BINDING + select HAVE_CF9_RESET config AMD_FP5 def_bool y if !AMD_FT5 @@ -225,6 +229,13 @@ config EARLYRAM_BSP_STACK_SIZE hex default 0x800 +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x40000 + help + The amount of coreboot-allocated heap and stack usage by the FSP. + menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS |