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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-04-04 02:37:04 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-04-29 05:38:08 +0000 |
| commit | 466732262817aadb1d9464883912112fd5d03fba (patch) | |
| tree | bda037f6df0ef07d400e71df516ef0b34de4a873 /src/soc/amd/picasso/Kconfig | |
| parent | ca928c6768ba143f619a99cca44f9f8153511270 (diff) | |
| download | coreboot-466732262817aadb1d9464883912112fd5d03fba.tar.xz | |
soc/amd/picasso: Add bootblock support
The original plan for Picasso was to combine the features of bootblock
with romstage due to its unique way of coming out of reset. Early in
development, all bootblock support was removed from the directory.
All Picasso designs will now use a bootblock as their first stage. The
reason being that it requires less invasive changes than using a hybrid
romstage.
Add a basic bootblock back to the directory, and compatible with the
design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM
and add appropriate settings in Kconfig. Make Makefile.inc calculates
the size and base of bootblock from known parameters.
* Future work may attempt to streamline this further, in conjunction
with changes in amdfwtool. See b/154957411.
BUG=b:147042464, b:153675909
Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3113b27783..afa18bc64c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES @@ -46,10 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC -config HAVE_BOOTBLOCK - bool - default n - config AMD_FP5 def_bool y if !AMD_FT5 help @@ -219,6 +216,14 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. +config X86_RESET_VECTOR + hex + default 0x807fff0 + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x800 + menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS |