diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-28 11:21:26 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-29 18:55:06 +0000 |
| commit | c6d89fba7a404684110a792a78dae86ec44b0738 (patch) | |
| tree | b47da55a1b944a5aad7e6ea57354acdf00014abb /src/soc/amd/picasso/Makefile.inc | |
| parent | 0c6abd786df61072f8dd2ec738bb05a5f8375775 (diff) | |
| download | coreboot-c6d89fba7a404684110a792a78dae86ec44b0738.tar.xz | |
soc/amd/picasso: Relocate FSP-M to address in DRAM
On Picasso, DRAM is up by the time FSP-M runs. This change relocates
FSP-M binary to a specific address (0x90000000) in DRAM. Currently,
this address is randomly chosen to ensure it does not overlap any of
the other stages. Once we have a unified memory map set up for
Picasso, this address can be updated along with it.
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046eaf10..d62ccda74d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -458,4 +458,6 @@ apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) + endif # ($(CONFIG_SOC_AMD_PICASSO),y) |