diff options
| author | Martin Roth <martinroth@chromium.org> | 2019-04-22 16:14:12 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-02 14:32:41 +0000 |
| commit | 778c8a77c1fc468b320f3471e7e753fd6f4afed7 (patch) | |
| tree | 1fc0cb9f3799f7e54ab995c80aa9ef45bcfe018e /src/soc/amd/picasso/Makefile.inc | |
| parent | d7e3ead8358ac76d432e26849951defb9ab28a9b (diff) | |
| download | coreboot-778c8a77c1fc468b320f3471e7e753fd6f4afed7.tar.xz | |
soc/amd/picasso: Stub out bootblock
Remove all Picasso bootblock support. CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage. Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index bb24c67b05..e8c022fcda 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -37,17 +37,12 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +# TODO: Make coreboot modifications so bootblock can be removed. This soc +# also selects C_ENVIRONMENT_BOOTBLOCK to enforce certain codepaths +# in romstage. As a result, the bootblock build also needs a +# dummy cache_as_ram.S +bootblock-y += cache_as_ram.S bootblock-y += bootblock/bootblock.c -bootblock-y += gpio.c -bootblock-y += i2c.c -bootblock-y += monotonic_timer.c -bootblock-y += pmutil.c -bootblock-y += reset.c -bootblock-y += tsc_freq.c -bootblock-y += southbridge.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += i2c.c romstage-y += romstage.c |