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| author | Martin Roth <martin@coreboot.org> | 2020-05-28 00:44:50 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2020-07-08 19:34:59 +0000 |
| commit | c7acf1666a517f0fcfec3a5f64791932ca145c45 (patch) | |
| tree | 8f2e6c0539a028ee3f2e27e5c80fe613678e7444 /src/soc/amd/picasso/Makefile.inc | |
| parent | ac41f582351dc2c6aaaf0c1ef662e6d99b67b4ce (diff) | |
| download | coreboot-c7acf1666a517f0fcfec3a5f64791932ca145c45.tar.xz | |
soc/amd/picasso: add psp_verstage
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9fe2..9ea770c86c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage bootblock-y += bootblock/pre_c.S bootblock-y += bootblock/bootblock.c @@ -21,11 +22,13 @@ bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c +bootblock-y += ../../../arch/x86/memmove.c romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c +romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c @@ -37,14 +40,15 @@ romstage-y += psp.c romstage-y += config.c romstage-y += mrc_cache.c -verstage-y += gpio.c verstage-y += i2c.c verstage-y += pmutil.c verstage-y += config.c verstage-y += aoac.c -verstage-y += uart.c -verstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -verstage-y += tsc_freq.c +verstage_x86-y += gpio.c +verstage_x86-y += uart.c +verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +verstage_x86-y += tsc_freq.c +verstage_x86-y += reset.c ramstage-y += i2c.c ramstage-y += chip.c @@ -58,6 +62,7 @@ ramstage-y += gpio.c ramstage-y += aoac.c ramstage-y += southbridge.c ramstage-y += pmutil.c +ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c ramstage-y += memmap.c @@ -75,8 +80,6 @@ ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c -all-y += reset.c - smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c |