summaryrefslogtreecommitdiff
path: root/src/soc/amd/picasso/Makefile.inc
diff options
context:
space:
mode:
authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-19 12:29:23 -0600
committerMartin Roth <martinroth@google.com>2019-09-09 22:20:08 +0000
commit80d0b01b38049775750c14cb0e0d978afb780ca1 (patch)
tree5290bc63262096e92359fc2319077ab748f8120f /src/soc/amd/picasso/Makefile.inc
parentba2533f0ee952a2bbe90ed60d5ab3d4c19513aa0 (diff)
downloadcoreboot-80d0b01b38049775750c14cb0e0d978afb780ca1.tar.xz
soc/amd/picasso: Update TSC and monotonic timer
Picasso's TimeStamp Counter is a new design and different than Stoney Ridge. Although advertised as invariant, the ST TSC did not become so until midway through POST making it an unreliable source for measuring time. This is not the case for Picasso. Remove the Stoney Ridge monotonic timer code and rely on the TSC. Modify the calculation used in Family 15h of finding the number of boost states first, and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
-rw-r--r--src/soc/amd/picasso/Makefile.inc4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 67d8904a13..ee9b407c53 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -40,7 +40,6 @@ subdirs-y += ../../../cpu/x86/smm
romstage-y += i2c.c
romstage-y += romstage.c
romstage-y += gpio.c
-romstage-y += monotonic_timer.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += smbus.c
@@ -53,7 +52,6 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
verstage-y += gpio.c
verstage-y += i2c.c
-verstage-y += monotonic_timer.c
verstage-y += pmutil.c
verstage-y += reset.c
verstage-$(CONFIG_PICASSO_UART) += uart.c
@@ -72,7 +70,6 @@ ramstage-y += cpu.c
ramstage-y += mca.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += gpio.c
-ramstage-y += monotonic_timer.c
ramstage-y += southbridge.c
ramstage-y += northbridge.c
ramstage-y += pmutil.c
@@ -89,7 +86,6 @@ ramstage-y += tsc_freq.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += finalize.c
-smm-y += monotonic_timer.c
smm-y += smihandler.c
smm-y += smi_util.c
smm-y += tsc_freq.c