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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-11 12:18:20 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:30:16 +0000 |
| commit | bc4c903c1f0bbf5297309082f31cfc2f70addb99 (patch) | |
| tree | 99924f3d876aad0b7d56dfd974ece168c5028c9f /src/soc/amd/picasso/Makefile.inc | |
| parent | 30cf1551683810504f7823e42d4cb6515459cff8 (diff) | |
| download | coreboot-bc4c903c1f0bbf5297309082f31cfc2f70addb99.tar.xz | |
soc/amd/picasso: Change all remaining soc names
Convert all remaining stoneyridge names to picasso.
Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e8c022fcda..b8a29c29a9 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -52,7 +52,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c romstage-y += ramtop.c -romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c @@ -63,12 +63,12 @@ verstage-y += i2c.c verstage-y += monotonic_timer.c verstage-y += pmutil.c verstage-y += reset.c -verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c -postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-$(CONFIG_PICASSO_UART) += uart.c postcar-y += ramtop.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -90,7 +90,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c @@ -117,7 +117,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ +PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) @@ -247,7 +247,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_SMUSCS_FILE) \ --combo-capable \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) @@ -255,23 +255,23 @@ PHONY+=add_amdfw INTERMEDIATE+=add_amdfw # Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ +PICASSO_FWM_ROM_POSITION=$(call int-add, \ $(call int-subtract, $(CONFIG_ROM_SIZE) \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(PICASSO_FWM_ROM_POSITION)" dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) |