diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-11 12:34:04 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:41:04 +0000 |
commit | 19ea0169108dc2eff743ae640a8108eb5852612d (patch) | |
tree | 90a9e0463572f14ae900b631495e7d55c26d61da /src/soc/amd/picasso/acpi/sb_pci0_fch.asl | |
parent | 7e5a2660bc927adac1fc420f94c111b8f8aae191 (diff) | |
download | coreboot-19ea0169108dc2eff743ae640a8108eb5852612d.tar.xz |
soc/amd/picasso: Remove most stoneyridge USB
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi/sb_pci0_fch.asl')
-rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3623814080..8cdb4d2750 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -208,27 +208,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { U2RP, 1, /* Usb2 Ref Clock Powerdown */ U3RP, 1, /* Usb3 Ref Clock Powerdown */ - /* XHCI_PM registers */ - offset (0x1c00), - , 1, - ,6, - U3PY, 1, - , 7, - UD3P, 1, /* bit 15 */ - U3PR, 1, /* bit 16 */ - , 11, - FWLM, 1, /* FirmWare Load Mode */ - FPLS, 1, /* Fw PreLoad Start */ - FPLC, 1, /* Fw PreLoad Complete */ - - offset (0x1c04), - UA04, 16, - , 15, - ROAM, 1, /* 1= ROM 0=RAM */ - - offset (0x1c08), - UA08, 32, - /* AOAC Registers */ offset (0x1e4a), /* I2C0 D3 Control */ I0TD, 2, @@ -442,8 +421,6 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(18) { U2D0()} /* EHCI */ - Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ Store(0x00, SDTD) Store(One, SDPD) @@ -505,8 +482,6 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(18) { U2D3()} /* EHCI */ - Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ Store(Zero, SDPD) Store(SDDS, Local0) @@ -541,26 +516,10 @@ Method(FDDC, 2, Serialized) Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { - FDDC(23, 3) - } - } - if(LNotEqual(U2TD, 0x03)) { - FDDC(18, 3) - } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { - FDDC(23, 0) - } - } - if(LEqual(U2TD, 0x03)) { - FDDC(18, 0) - } if(LEqual(\UT0E, zero)) { if(LNotEqual(U0TD, 0x03)) { FDDC(11, 3) |