diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-12-14 16:55:09 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-06 17:26:30 +0000 |
| commit | 2f5fd1147442978264f062422812ec12f64a23a5 (patch) | |
| tree | cbcfb771d8e9da6f7ceeb6fa58412c74629ead72 /src/soc/amd/picasso/acpi | |
| parent | 9541d1792a38c4e500edb1de0570002355423808 (diff) | |
| download | coreboot-2f5fd1147442978264f062422812ec12f64a23a5.tar.xz | |
soc/amd/picasso: Fix ACPI PCI routing table
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly
generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.
BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/acpi')
| -rw-r--r-- | src/soc/amd/picasso/acpi/northbridge.asl | 12 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/pci_int.asl | 4 |
2 files changed, 4 insertions, 12 deletions
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index a81d3b27be..f6e198f5f2 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -26,18 +26,6 @@ Name(PR0, Package(){ Package() { 0x0000FFFF, 0, INTC, 0 }, Package() { 0x0000FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridges */ - Package() { 0x0001FFFF, 0, INTA, 0 }, - Package() { 0x0001FFFF, 1, INTB, 0 }, - Package() { 0x0001FFFF, 2, INTC, 0 }, - Package() { 0x0001FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 0x08 - F[1:PCI Bridge to Bus A, 2: PCI Bridge to Bus B] */ - Package() { 0x0008FFFF, 0, INTA, 0 }, - Package() { 0x0008FFFF, 1, INTB, 0 }, - Package() { 0x0008FFFF, 2, INTC, 0 }, - Package() { 0x0008FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 0x14 - F[0:SMBus 3:LPC] */ Package() { 0x0014FFFF, 0, INTA, 0 }, Package() { 0x0014FFFF, 1, INTB, 0 }, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 8114c52043..feaec12d29 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -104,3 +104,7 @@ PCI_LINK(INTA, PIRA, IORA) PCI_LINK(INTB, PIRB, IORB) PCI_LINK(INTC, PIRC, IORC) PCI_LINK(INTD, PIRD, IORD) +PCI_LINK(INTE, PIRE, IORE) +PCI_LINK(INTF, PIRF, IORF) +PCI_LINK(INTG, PIRG, IORG) +PCI_LINK(INTH, PIRH, IORH) |