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authorRaul E Rangel <rrangel@chromium.org>2020-05-28 15:29:01 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-06-03 12:15:54 +0000
commitf700be00e926a6ac3d2b32b63105ea15eb5ef8e5 (patch)
tree5e99c6ba6e17ef72f29e3cd419f2815485c47c9a /src/soc/amd/picasso/acpi
parent27b6b0ed72bbb7ba36096a5c278a416b0bc84f65 (diff)
downloadcoreboot-f700be00e926a6ac3d2b32b63105ea15eb5ef8e5.tar.xz
soc/amd/picasso/acpi: Add missing eMMC device
BUG=b:154756391 TEST=Boot trembyle and see that /dev/mmcblk1 now exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi')
-rw-r--r--src/soc/amd/picasso/acpi/pcie.asl6
-rw-r--r--src/soc/amd/picasso/acpi/sb_fch.asl35
2 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl
index 561a3f8140..954c536539 100644
--- a/src/soc/amd/picasso/acpi/pcie.asl
+++ b/src/soc/amd/picasso/acpi/pcie.asl
@@ -16,6 +16,9 @@
PIRG, 0x00000008, /* Index 6: INTG */
PIRH, 0x00000008, /* Index 7: INTH */
+ Offset (0x43),
+ PMMC, 0x00000008, /* Index 0x43: eMMC */
+
Offset (0x62),
PGPI, 0x00000008, /* Index 0x62: GPIO */
@@ -42,6 +45,9 @@
IORG, 0x00000008, /* Index 0x86: INTG */
IORH, 0x00000008, /* Index 0x87: INTH */
+ Offset (0xC3),
+ IMMC, 0x00000008, /* Index 0xC3: eMMC */
+
Offset (0xE2),
IGPI, 0x00000008, /* Index 0xE2: GPIO */
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
index c5316482e5..a7f60c2424 100644
--- a/src/soc/amd/picasso/acpi/sb_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -57,6 +57,41 @@ Device (GPIO)
}
}
+Device (MMC0)
+{
+ Name (_HID, "AMDI0040")
+ Name (_UID, 0x0)
+ Method (_CRS, 0) {
+ Name (RBUF, ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Level,
+ ActiveLow,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+ })
+ CreateDWordField (RBUF, IRQR._INT, IRQN)
+ If (PMOD) {
+ IRQN = IMMC
+ } Else {
+ IRQN = PMMC
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate(){
+ Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+ })
+ } Else {
+ Return (RBUF)
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
Device (FUR0)
{
Name (_HID, "AMD0020")