summaryrefslogtreecommitdiff
path: root/src/soc/amd/picasso/chip.h
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2020-08-28 01:40:20 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-31 06:42:39 +0000
commit82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf (patch)
tree9a0e004c6ccd4e236440bb848fcb2bf78c605860 /src/soc/amd/picasso/chip.h
parent05ef94795f0303326084290690659f99c6c0e9a7 (diff)
downloadcoreboot-82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf.tar.xz
soc/amd/picasso/southbridge: make GPP clock outputs configurable
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/chip.h')
-rw-r--r--src/soc/amd/picasso/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index b641379605..ac1a12c6b1 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -154,6 +154,9 @@ struct soc_amd_picasso_config {
USB_OC_PIN_5 = 0x5,
USB_OC_NONE = 0xf,
} usb_port_overcurrent_pin[USB_PORT_COUNT];
+
+ /* The array index is the general purpose PCIe clock output number. */
+ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
};
typedef struct soc_amd_picasso_config config_t;