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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-04-19 13:47:36 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-04-29 14:51:47 +0000
commit6fcc46d1a41d8818e1dc791cadd173fd05afe54b (patch)
tree4bc09cccbf0166c15d04c332d414c652d7e2e270 /src/soc/amd/picasso/chip.h
parent4a5057d8fa0cf5651e896f4386c031e2671e78b5 (diff)
downloadcoreboot-6fcc46d1a41d8818e1dc791cadd173fd05afe54b.tar.xz
cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS
Some platforms which have large amounts of RAM and also write-combining regions may decide to drop the WC regions in favor of the default when preserving MTRRs for the OS. From a data safety perspective, this is safe to do, but if, say, the graphics framebuffer is the region that is changed from WC to UC/WB, then the performance of writing to the framebuffer will decrease dramatically. Modern OSes typically use Page Attribute Tables (PAT) to determine the cacheability on a page level and usually do not touch the MTRRs. Thus, it is believed to be safe to stop reserving MTRRs for the OS, in general; PentiumII is the exception here in that OSes that still support that may still require MTRRs to be available. In any case, if the OS wants to reprogram all of the MTRRs, it is of course still free to do so (after consulting the e820 table). BUG=b:185452338 TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources` was faked to think it had 32 GiB of DRAM installed) and variable MTRR map includes a WC entry for the framebuffer (and all the RAM): MTRR: default type WB/UC MTRR counts: 13/9. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0 MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6 MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0 ADL has 9 variable-range MTRRs, previously 8 of them were used, and there was no separate entry for the framebuffer, thus leaving the default MTRR in place of uncached. Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/chip.h')
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