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| author | Matt DeVillier <matt.devillier@gmail.com> | 2019-08-24 23:54:41 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-26 13:45:32 +0000 |
| commit | 4af1fe23f8658ec51380b68ecdd317ddc1dfb854 (patch) | |
| tree | e108c09a0ce736d9f145c76ff86175b0a9008fef /src/soc/amd/picasso/i2c.c | |
| parent | a5d9e7a62884d4a1121795f928232fe13431b769 (diff) | |
| download | coreboot-4af1fe23f8658ec51380b68ecdd317ddc1dfb854.tar.xz | |
google/link: fix detection of dimm on channel 1
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.
Test: boot google/link, observe onboard RAM correctly
detected on both channels
Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/amd/picasso/i2c.c')
0 files changed, 0 insertions, 0 deletions