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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-09-04 12:07:27 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-09-10 12:37:45 +0000 |
| commit | 39c64b0bdd04a84bf206be5a94ceb1d685e9e1a8 (patch) | |
| tree | e8a475836ed5567c464edb026d6ca9ee48b4e48c /src/soc/amd/picasso/include/soc/iomap.h | |
| parent | 39a8040ddc551306d823d52a459fdb5dd717b2fe (diff) | |
| download | coreboot-39c64b0bdd04a84bf206be5a94ceb1d685e9e1a8.tar.xz | |
soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 825683653a..890b1c3647 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -5,6 +5,7 @@ /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 #if CONFIG(HPET_ADDRESS_OVERRIDE) |