diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-13 15:59:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:57:10 +0000 |
| commit | 9df03a168fd54bc8e872448ff9fdfa30313c40ba (patch) | |
| tree | 77ef54a8c620b19ea4fc35a58d88e36db53e49a0 /src/soc/amd/picasso/include/soc/southbridge.h | |
| parent | a392b00131d1ddc8489bf24c2eb7a14300374680 (diff) | |
| download | coreboot-9df03a168fd54bc8e872448ff9fdfa30313c40ba.tar.xz | |
soc/amd/picasso: Remove all PSP runtime functions
Remove the mailbox call to notify the PSP that DRAM is ready. This
is not supported on Family 17h.
Remove the selectable SMU firmware. This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.
Clean up additional mentions of PSP within picasso.
Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0f72a68567..b28522e60f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -277,11 +277,6 @@ #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) -/* Platform Security Processor D8F0 */ -#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_BAR_ENABLES 0x48 -#define PSP_MAILBOX_BAR_EN 0x10 - /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) |