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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-28 01:40:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-31 06:42:39 +0000 |
| commit | 82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf (patch) | |
| tree | 9a0e004c6ccd4e236440bb848fcb2bf78c605860 /src/soc/amd/picasso/include | |
| parent | 05ef94795f0303326084290690659f99c6c0e9a7 (diff) | |
| download | coreboot-82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf.tar.xz | |
soc/amd/picasso/southbridge: make GPP clock outputs configurable
Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.
BUG=b:149970243
BRANCH=zork
Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b5792139da..168b2b2e22 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -245,6 +245,13 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ +/* this is for the devicetree setting and not the values written to the register */ +enum gpp_clk_req_setting { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ +}; + typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ |