diff options
| author | Martin Roth <martinroth@chromium.org> | 2020-02-05 16:46:30 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 19:08:08 +0000 |
| commit | 86ba0d73f34185533e5e2d4258aa3bf3dba40ed4 (patch) | |
| tree | 5b2f8f95c783997eee1f1aad0049559a71ebc7cb /src/soc/amd/picasso/include | |
| parent | 33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e (diff) | |
| download | coreboot-86ba0d73f34185533e5e2d4258aa3bf3dba40ed4.tar.xz | |
soc/amd/picasso/graphics: implement map_oprom_vendev_rev
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need
different video BIOSes. This checks the vendor & device IDs along with
the revision and selects the correct video BIOS to use.
Also add the second VGA BIOS for Raven2-based SoCs and change all VGA
BIOS IDs to the format including the revision number.
Since SeaBIOS still expects the CBFS file name without the revision ID,
it won't find the VBIOS any more. As a temporary workaround add the
VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*.
Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index fd9c5fee48..e79dd87faf 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -12,4 +12,9 @@ void check_mca(void); #define RAVEN2_A0_CPUID 0x00820f00 #define RAVEN2_A1_CPUID 0x00820f01 +#define PICASSO_VBIOS_VID_DID 0x100215d8 +#define PICASSO_VBIOS_REV 0xc1 +#define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ +#define RAVEN2_VBIOS_REV 0xc4 + #endif /* __PICASSO_CPU_H__ */ |