soc/amd/picasso: Create picasso as a copy of stoneyridge

So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way.  We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.

Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is  updated.

Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 1692 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h
new file mode 100644
index 0000000000..15a41edce6
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/acpi.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_STONEYRIDGE_ACPI_H__
+#define __SOC_STONEYRIDGE_ACPI_H__
+
+#include <arch/acpi.h>
+
+#if CONFIG(STONEYRIDGE_LEGACY_FREE)
+	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
+#else
+	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
+#endif
+
+#ifndef FADT_PM_PROFILE
+	#define FADT_PM_PROFILE PM_UNSPECIFIED
+#endif
+
+unsigned long southbridge_write_acpi_tables(struct device *device,
+		unsigned long current, struct acpi_rsdp *rsdp);
+
+void southbridge_inject_dsdt(struct device *device);
+
+const char *soc_acpi_name(const struct device *dev);
+
+#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h
new file mode 100644
index 0000000000..beef2bcc81
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMD_PCI_INT_DEFS_H__
+#define __AMD_PCI_INT_DEFS_H__
+
+/*
+ * PIRQ and device routing - these define the index into the
+ * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
+ */
+
+#define PIRQ_NC		0x1f	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_MISC1	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
+#define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
+#define PIRQ_SIRQD	0x0f	/* Serial IRQ INTD */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
+#define PIRQ_ASF	0x12	/* ASF */
+#define PIRQ_HDA	0x13	/* HDA		14h.2 */
+#define PIRQ_FC		0x14	/* FC */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+#define PIRQ_SD		0x17	/* SD */
+#define PIRQ_SDIO	0x1a	/* SDIO */
+#define PIRQ_EHCI	0x30	/* USB EHCI	12h.0 */
+#define PIRQ_XHCI	0x34	/* USB XHCI	10h.0 */
+#define PIRQ_SATA	0x41	/* SATA		11h.0 */
+#define PIRQ_GPIO	0x62	/* GPIO Controller Interrupt */
+#define PIRQ_I2C0	0x70
+#define PIRQ_I2C1	0x71
+#define PIRQ_I2C2	0x72
+#define PIRQ_I2C3	0x73
+#define PIRQ_UART0	0x74
+#define PIRQ_UART1	0x75
+
+#endif /* __AMD_PCI_INT_DEFS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
new file mode 100644
index 0000000000..934a9f2983
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_CPU_H__
+#define __STONEYRIDGE_CPU_H__
+
+#include <device/device.h>
+
+/*
+ *  Set a variable MTRR in bootblock and/or romstage.  AGESA will use the lowest
+ *  numbered registers.  Any values defined below are subtracted from the
+ *  highest numbered registers.
+ *
+ *  todo: Revisit this once AGESA no longer programs MTRRs.
+ */
+#define SOC_EARLY_VMTRR_FLASH 1
+#define SOC_EARLY_VMTRR_CAR_HEAP 2
+#define SOC_EARLY_VMTRR_TEMPRAM 3
+
+void stoney_init_cpus(struct device *dev);
+void check_mca(void);
+
+#endif /* __STONEYRIDGE_CPU_H__ */
diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h
new file mode 100644
index 0000000000..d8774f051a
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/gpio.h
@@ -0,0 +1,308 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_GPIO_H__
+#define __STONEYRIDGE_GPIO_H__
+
+#define GPIO_DEVICE_NAME	"AMD0030"
+#define GPIO_DEVICE_DESC	"GPIO Controller"
+
+#ifndef __ACPI__
+#include <soc/iomap.h>
+#include <amdblocks/gpio_banks.h>
+
+/* The following sections describe only the GPIOs defined for this SOC */
+
+#define SOC_GPIO_TOTAL_PINS		149
+
+/* Bank 0: GPIO_0 - GPIO_62 */
+#define GPIO_0				0
+#define GPIO_1				1
+#define GPIO_2				2
+#define GPIO_3				3
+#define GPIO_4				4
+#define GPIO_5				5
+#define GPIO_6				6
+#define GPIO_7				7
+#define GPIO_8				8
+#define GPIO_9				9
+#define GPIO_10				10
+#define GPIO_11				11
+#define GPIO_12				12
+#define GPIO_13				13
+#define GPIO_14				14
+#define GPIO_15				15
+#define GPIO_16				16
+#define GPIO_17				17
+#define GPIO_18				18
+#define GPIO_19				19
+#define GPIO_20				20
+#define GPIO_21				21
+#define GPIO_22				22
+#define GPIO_23				23
+#define GPIO_24				24
+#define GPIO_25				25
+#define GPIO_26				26
+#define GPIO_39				39
+#define GPIO_40				40
+#define GPIO_42				42
+
+/* Bank 1: GPIO_64 - GPIO_127 */
+#define GPIO_64				64
+#define GPIO_65				65
+#define GPIO_66				66
+#define GPIO_67				67
+#define GPIO_68				68
+#define GPIO_69				69
+#define GPIO_70				70
+#define GPIO_71				71
+#define GPIO_72				72
+#define GPIO_74				74
+#define GPIO_75				75
+#define GPIO_76				76
+#define GPIO_84				84
+#define GPIO_85				85
+#define GPIO_86				86
+#define GPIO_87				87
+#define GPIO_88				88
+#define GPIO_89				89
+#define GPIO_90				90
+#define GPIO_91				91
+#define GPIO_92				92
+#define GPIO_93				93
+#define GPIO_95				95
+#define GPIO_96				96
+#define GPIO_97				97
+#define GPIO_98				98
+#define GPIO_99				99
+#define GPIO_100			100
+#define GPIO_101			101
+#define GPIO_102			102
+#define GPIO_113			113
+#define GPIO_114			114
+#define GPIO_115			115
+#define GPIO_116			116
+#define GPIO_117			117
+#define GPIO_118			118
+#define GPIO_119			119
+#define GPIO_120			120
+#define GPIO_121			121
+#define GPIO_122			122
+#define GPIO_126			126
+
+/* Bank 2: GPIO_128 - GPIO_183 */
+#define GPIO_129			129
+#define GPIO_130			130
+#define GPIO_131			131
+#define GPIO_132			132
+#define GPIO_133			133
+#define GPIO_134			134
+#define GPIO_135			135
+#define GPIO_136			136
+#define GPIO_137			137
+#define GPIO_138			138
+#define GPIO_139			139
+#define GPIO_140			140
+#define GPIO_141			141
+#define GPIO_142			142
+#define GPIO_143			143
+#define GPIO_144			144
+#define GPIO_145			145
+#define GPIO_146			146
+#define GPIO_147			147
+#define GPIO_148			148
+
+#define GPIO_SCL_HIGH			0
+#define GPIO_SCL_LOW			GPIO_OUTPUT_ENABLE
+
+/* IOMUX function names and values generated from BKDG. */
+#define GPIO_0_IOMUX_PWR_BTN_L 0
+#define GPIO_0_IOMUX_GPIOxx 1
+#define GPIO_1_IOMUX_SYS_RESET_L 0
+#define GPIO_1_IOMUX_GPIOxx 1
+#define GPIO_2_IOMUX_WAKE_L 0
+#define GPIO_2_IOMUX_GPIOxx 1
+#define GPIO_3_IOMUX_GPIOxx 0
+#define GPIO_4_IOMUX_GPIOxx 0
+#define GPIO_5_IOMUX_GPIOxx 0
+#define GPIO_5_IOMUX_DEVSLP0_S5 1
+#define GPIO_6_IOMUX_GPIOxx 0
+#define GPIO_6_IOMUX_LDT_RST_L 1
+#define GPIO_7_IOMUX_GPIOxx 0
+#define GPIO_7_IOMUX_LDT_PWROK 1
+#define GPIO_8_IOMUX_GPIOxx 0
+#define GPIO_8_IOMUX_SerPortTX_OUT 1
+#define GPIO_9_IOMUX_GPIOxx 0
+#define GPIO_9_IOMUX_SerPortRX_OUT 1
+#define GPIO_10_IOMUX_S0A3_GPIO 0
+#define GPIO_10_IOMUX_GPIOxx 1
+#define GPIO_11_IOMUX_GPIOxx 0
+#define GPIO_11_IOMUX_USB_OC7_L 1
+#define GPIO_12_IOMUX_IR_LED_L 0
+#define GPIO_12_IOMUX_LLB_L 1
+#define GPIO_12_IOMUX_GPIOxx 2
+#define GPIO_13_IOMUX_USB_OC5_L 0
+#define GPIO_13_IOMUX_GPIOxx 1
+#define GPIO_14_IOMUX_USB_OC6_L 0
+#define GPIO_14_IOMUX_GPIOxx 1
+#define GPIO_15_IOMUX_IR_RX1 0
+#define GPIO_15_IOMUX_GPIOxx 1
+#define GPIO_16_IOMUX_USB_OC0_L 0
+#define GPIO_16_IOMUX_TRST_L 1
+#define GPIO_16_IOMUX_GPIOxx 2
+#define GPIO_17_IOMUX_USB_OC1_L 0
+#define GPIO_17_IOMUX_TDI 1
+#define GPIO_17_IOMUX_GPIOxx 2
+#define GPIO_18_IOMUX_USB_OC2_L 0
+#define GPIO_18_IOMUX_TCK 1
+#define GPIO_18_IOMUX_GPIOxx 2
+#define GPIO_19_IOMUX_SCL1 0
+#define GPIO_19_IOMUX_I2C3_SCL 1
+#define GPIO_19_IOMUX_GPIOxx 2
+#define GPIO_20_IOMUX_SDA1 0
+#define GPIO_20_IOMUX_I2C3_SDA 1
+#define GPIO_20_IOMUX_GPIOxx 2
+#define GPIO_21_IOMUX_LPC_PD_L 0
+#define GPIO_21_IOMUX_GPIOxx 1
+#define GPIO_22_IOMUX_LPC_PME_L 0
+#define GPIO_22_IOMUX_GPIOxx 1
+#define GPIO_23_IOMUX_USB_OC4_L 0
+#define GPIO_23_IOMUX_IR_RX0 1
+#define GPIO_23_IOMUX_GPIOxx 2
+#define GPIO_24_IOMUX_USB_OC3_L 0
+#define GPIO_24_IOMUX_GPIOxx 1
+#define GPIO_25_IOMUX_SD0_CD 0
+#define GPIO_25_IOMUX_GPIOxx 1
+#define GPIO_26_IOMUX_PCIE_RST_L 0
+#define GPIO_26_IOMUX_GPIOxx 1
+#define GPIO_39_IOMUX_VDDGFX_PD 0
+#define GPIO_39_IOMUX_GPIOxx 1
+#define GPIO_40_IOMUX_GPIOxx 0
+#define GPIO_42_IOMUX_S5_MUX_CTRL 0
+#define GPIO_42_IOMUX_GPIOxx 1
+#define GPIO_64_IOMUX_GPIOxx 0
+#define GPIO_65_IOMUX_GPIOxx 0
+#define GPIO_66_IOMUX_GPIOxx 0
+#define GPIO_67_IOMUX_GPIOxx 0
+#define GPIO_67_IOMUX_DEVSLP0 1
+#define GPIO_69_IOMUX_GPIOxx 0
+#define GPIO_69_IOMUX_SGPIO_LOAD 1
+#define GPIO_70_IOMUX_GPIOxx 0
+#define GPIO_70_IOMUX_DEVSLP1 1
+#define GPIO_74_IOMUX_LPCCLK0 0
+#define GPIO_74_IOMUX_GPIOxx 1
+#define GPIO_75_IOMUX_LPCCLK1 0
+#define GPIO_75_IOMUX_GPIOxx 1
+#define GPIO_76_IOMUX_GPIOxx 0
+#define GPIO_76_IOMUX_SPI_TPM_CS_L 1
+#define GPIO_84_IOMUX_FANIN0 0
+#define GPIO_84_IOMUX_GPIOxx 1
+#define GPIO_85_IOMUX_FANOUT0 0
+#define GPIO_85_IOMUX_GPIOxx 1
+#define GPIO_86_IOMUX_GPIOxx 1
+#define GPIO_87_IOMUX_SERIRQ 0
+#define GPIO_87_IOMUX_GPIOxx 1
+#define GPIO_88_IOMUX_LPC_CLKRUN_L 0
+#define GPIO_88_IOMUX_GPIOxx 1
+#define GPIO_90_IOMUX_GPIOxx 0
+#define GPIO_91_IOMUX_SPKR 0
+#define GPIO_91_IOMUX_GPIOxx 1
+#define GPIO_92_IOMUX_CLK_REQ0_L 0
+#define GPIO_92_IOMUX_SATA_IS0_L 1
+#define GPIO_92_IOMUX_SATA_ZP0_L 2
+#define GPIO_92_IOMUX_GPIOxx 3
+#define GPIO_93_IOMUX_SD0_LED 0
+#define GPIO_93_IOMUX_GPIOxx 1
+#define GPIO_95_IOMUX_GPIOxx 0
+#define GPIO_96_IOMUX_GPIOxx 0
+#define GPIO_97_IOMUX_GPIOxx 0
+#define GPIO_98_IOMUX_GPIOxx 0
+#define GPIO_99_IOMUX_GPIOxx 0
+#define GPIO_100_IOMUX_GPIOxx 0
+#define GPIO_101_IOMUX_SD0_WP 0
+#define GPIO_101_IOMUX_GPIOxx 1
+#define GPIO_102_IOMUX_SD0_PWR_CTRL 0
+#define GPIO_102_IOMUX_GPIOxx 1
+#define GPIO_113_IOMUX_SCL0 0
+#define GPIO_113_IOMUX_I2C2_SCL 1
+#define GPIO_113_IOMUX_GPIOxx 2
+#define GPIO_114_IOMUX_SDA0 0
+#define GPIO_114_IOMUX_I2C2_SDA 1
+#define GPIO_114_IOMUX_GPIOxx 2
+#define GPIO_115_IOMUX_CLK_REQ1_L 0
+#define GPIO_115_IOMUX_GPIOxx 1
+#define GPIO_116_IOMUX_CLK_REQ2_L 0
+#define GPIO_116_IOMUX_GPIOxx 1
+#define GPIO_117_IOMUX_ESPI_CLK 0
+#define GPIO_117_IOMUX_GPIOxx 1
+#define GPIO_118_IOMUX_SPI_CS1_L 0
+#define GPIO_118_IOMUX_GPIOxx 1
+#define GPIO_119_IOMUX_SPI_CS2_L 0
+#define GPIO_119_IOMUX_ESPI_CS_L 1
+#define GPIO_119_IOMUX_GPIOxx 2
+#define GPIO_120_IOMUX_ESPI_DAT1 0
+#define GPIO_120_IOMUX_GPIOxx 1
+#define GPIO_121_IOMUX_ESPI_DAT0 0
+#define GPIO_121_IOMUX_GPIOxx 1
+#define GPIO_122_IOMUX_ESPI_DAT2 0
+#define GPIO_122_IOMUX_GPIOxx 1
+#define GPIO_126_IOMUX_GA20IN 0
+#define GPIO_126_IOMUX_GPIOxx 1
+#define GPIO_129_IOMUX_KBRST_L 0
+#define GPIO_129_IOMUX_GPIOxx 1
+#define GPIO_130_IOMUX_SATA_ACT_L 0
+#define GPIO_130_IOMUX_GPIOxx 1
+#define GPIO_131_IOMUX_CLK_REQ3_L 0
+#define GPIO_131_IOMUX_SATA_IS1_L 1
+#define GPIO_131_IOMUX_SATA_ZP1_L 2
+#define GPIO_131_IOMUX_GPIOxx 3
+#define GPIO_132_IOMUX_CLK_REQG_L 0
+#define GPIO_132_IOMUX_OSCIN 1
+#define GPIO_132_IOMUX_GPIOxx 2
+#define GPIO_133_IOMUX_ESPI_DAT3 0
+#define GPIO_133_IOMUX_GPIOxx 1
+#define GPIO_135_IOMUX_UART0_CTS_L 0
+#define GPIO_135_IOMUX_GPIOxx 1
+#define GPIO_136_IOMUX_UART0_RXD 0
+#define GPIO_136_IOMUX_GPIOxx 1
+#define GPIO_137_IOMUX_UART0_RTS_L 0
+#define GPIO_137_IOMUX_GPIOxx 1
+#define GPIO_138_IOMUX_UART0_TXD 0
+#define GPIO_138_IOMUX_GPIOxx 1
+#define GPIO_139_IOMUX_UART0_INTR 0
+#define GPIO_139_IOMUX_GPIOxx 1
+#define GPIO_140_IOMUX_UART1_CTS_L 0
+#define GPIO_140_IOMUX_GPIOxx 1
+#define GPIO_141_IOMUX_UART1_RXD 0
+#define GPIO_141_IOMUX_GPIOxx 1
+#define GPIO_142_IOMUX_UART1_RTS_L 0
+#define GPIO_142_IOMUX_GPIOxx 1
+#define GPIO_143_IOMUX_UART1_TXD 0
+#define GPIO_143_IOMUX_GPIOxx 1
+#define GPIO_144_IOMUX_UART1_INTR 0
+#define GPIO_144_IOMUX_GPIOxx 1
+#define GPIO_145_IOMUX_I2C0_SCL 0
+#define GPIO_145_IOMUX_GPIOxx 1
+#define GPIO_146_IOMUX_I2C0_SDA 0
+#define GPIO_146_IOMUX_GPIOxx 1
+#define GPIO_147_IOMUX_I2C1_SCL 0
+#define GPIO_147_IOMUX_GPIOxx 1
+#define GPIO_148_IOMUX_I2C1_SDA 0
+#define GPIO_148_IOMUX_GPIOxx 1
+
+#define GPIO_2_EVENT GEVENT_8
+
+#endif /* __ACPI__ */
+#endif /* __STONEYRIDGE_GPIO_H__ */
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h
new file mode 100644
index 0000000000..62575d0fb8
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/i2c.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_I2C_H__
+#define __STONEYRIDGE_I2C_H__
+
+#include <soc/gpio.h>
+
+struct soc_amd_i2c_save {
+	uint32_t control_value;
+	uint8_t mux_value;
+};
+
+#define GPIO_I2C0_SCL			BIT(0)
+#define GPIO_I2C1_SCL			BIT(1)
+#define GPIO_I2C2_SCL			BIT(2)
+#define GPIO_I2C3_SCL			BIT(3)
+#define GPIO_I2C_MASK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+#define I2C0_SCL_PIN			GPIO_145
+#define I2C1_SCL_PIN			GPIO_147
+#define I2C2_SCL_PIN			GPIO_113
+#define I2C3_SCL_PIN			GPIO_19
+
+#define GPIO_I2C0_ADDRESS		GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
+#define GPIO_I2C1_ADDRESS		GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
+#define GPIO_I2C2_ADDRESS		GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
+#define GPIO_I2C3_ADDRESS		GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
+
+#define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
+#define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
+#define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_113_IOMUX_GPIOxx
+#define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
+
+void sb_reset_i2c_slaves(void);
+
+#endif /* __STONEYRIDGE_I2C_H__ */
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
new file mode 100644
index 0000000000..612b6e871b
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Raptor Engineering, LLC
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_STONEYRIDGE_IOMAP_H__
+#define __SOC_STONEYRIDGE_IOMAP_H__
+
+/* MMIO Ranges */
+#define PSP_MAILBOX_BAR3_BASE		0xf0a00000
+#define SPI_BASE_ADDRESS		0xfec10000
+#define IO_APIC2_ADDR			0xfec20000
+
+/*
+ * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1].
+ * All ranges not specified as supported below may, or may not, be listed in
+ * any documentation but should be considered reserved through FED8_1FFFh.
+ */
+#include <amdblocks/acpimmio_map.h>
+#define SUPPORTS_ACPIMMIO_SMI_BASE	1 /* 0xfed80100 */
+#define SUPPORTS_ACPIMMIO_PMIO_BASE	1 /* 0xfed80300 */
+#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE	1 /* 0xfed80500 */
+#define SUPPORTS_ACPIMMIO_ACPI_BASE	1 /* 0xfed80800 */
+#define SUPPORTS_ACPIMMIO_ASF_BASE	1 /* 0xfed80900 */
+#define SUPPORTS_ACPIMMIO_SMBUS_BASE	1 /* 0xfed80a00 */
+#define SUPPORTS_ACPIMMIO_IOMUX_BASE	1 /* 0xfed80d00 */
+#define SUPPORTS_ACPIMMIO_MISC_BASE	1 /* 0xfed80e00 */
+#define SUPPORTS_ACPIMMIO_GPIO0_BASE	1 /* 0xfed81500 */
+#define SUPPORTS_ACPIMMIO_GPIO1_BASE	1 /* 0xfed81800 */
+#define SUPPORTS_ACPIMMIO_GPIO2_BASE	1 /* 0xfed81700 */
+#define SUPPORTS_ACPIMMIO_XHCIPM_BASE	1 /* 0xfed81c00 */
+#define SUPPORTS_ACPIMMIO_AOAC_BASE	1 /* 0xfed81e00 */
+
+#define ALINK_AHB_ADDRESS		0xfedc0000
+
+/* I2C fixed address */
+#define I2C_BASE_ADDRESS		0xfedc2000
+#define I2C_DEVICE_SIZE			0x00001000
+#define I2C_DEVICE_COUNT		4
+
+#if CONFIG(HPET_ADDRESS_OVERRIDE)
+#error HPET address override is not allowed and must be fixed at 0xfed00000
+#endif
+#define HPET_BASE_ADDRESS		0xfed00000
+
+#define APU_UART0_BASE			0xfedc6000
+#define APU_UART1_BASE			0xfedc8000
+
+#define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
+
+/* I/O Ranges */
+#define ACPI_SMI_CTL_PORT		0xb2
+#define STONEYRIDGE_ACPI_IO_BASE	CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define  ACPI_PM_EVT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define  ACPI_PM1_STS		(ACPI_PM_EVT_BLK + 0x00)	  /* 2 bytes */
+#define  ACPI_PM1_EN		(ACPI_PM_EVT_BLK + 0x02)	  /* 2 bytes */
+#define  ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define  ACPI_CPU_CONTROL	(STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
+#define  ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define  ACPI_GPE0_STS		(ACPI_GPE0_BLK + 0x00)		  /* 4 bytes */
+#define  ACPI_GPE0_EN		(ACPI_GPE0_BLK + 0x04)		  /* 4 bytes */
+#define  ACPI_PM_TMR_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define SMB_BASE_ADDR			0xb00
+#define PM2_INDEX			0xcd0
+#define PM2_DATA			0xcd1
+#define BIOSRAM_INDEX			0xcd4
+#define BIOSRAM_DATA			0xcd5
+#define AB_INDX				0xcd8
+#define AB_DATA				(AB_INDX+4)
+#define SYS_RESET			0xcf9
+
+/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
+#define BIOSRAM_CBMEM_TOP		0xf0 /* 4 bytes */
+#define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
+#define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
+
+#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
new file mode 100644
index 0000000000..60a6ea22bb
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
+
+#include <device/device.h>
+#include <types.h>
+
+/* D0F0 - Root Complex */
+
+/* NB IOAPIC registers */
+#define NB_IOAPIC_INDEX		0xf8
+#define NB_IOAPIC_DATA		0xfc
+#define  NB_IOAPIC_FEATURE_CTRL	0x00
+#define  NB_IOAPIC_ADDRESS_LOW	0x01
+#define  NB_IOAPIC_ADDRESS_HIGH	0x02
+#define  NB_IOAPIC_GBIF_IRR	0x0f
+#define  NB_IOAPIC_BR0_IRR	0x10
+#define  NB_IOAPIC_BR1_IRR	0x11
+#define  NB_IOAPIC_BR2_IRR	0x12
+#define  NB_IOAPIC_BR3_IRR	0x13
+#define  NB_IOAPIC_BR4_IRR	0x14
+#define  NB_IOAPIC_APG_IRR	0x2f
+#define  NB_IOAPIC_SPG_IRR	0x30
+#define  NB_IOAPIC_SER_IRQ_IRR	0x31
+#define  NB_IOAPIC_SCRATCH0	0x3e
+#define  NB_IOAPIC_SCRATCH1	0x3f
+
+#define AP_SCRATCH_REG		NB_IOAPIC_SCRATCH0
+
+/* D1F1 - HDA Configuration Registers */
+#define HDA_DEV_CTRL_STATUS	0x60
+#define   HDA_NO_SNOOP_EN	BIT(11)
+
+/* D18F0 - HT Configuration Registers */
+#define D18F0_NODE_ID		0x60
+#define D18F0_CPU_CNT		0x62 /* BKDG defines as a field in DWORD 0x60 */
+# define CPU_CNT_MASK		0x1f /*  CpuCnt + 1 = no. CPUs */
+#define HT_INIT_CONTROL		0x6c
+# define HTIC_BIOSR_DETECT	((1 << 5) | (1 << 9) | (1 << 10))
+# define HTIC_COLD_RST_DET	BIT(4)
+
+/* D18F1 - Address Map Registers */
+
+/* MMIO base and limit */
+#define D18F1_MMIO_BASE0_LO	0x80
+# define MMIO_WE		(1 << 1)
+# define MMIO_RE		(1 << 0)
+#define D18F1_MMIO_LIMIT0_LO	0x84
+# define MMIO_NP		(1 << 7)
+#define D18F1_IO_BASE0_LO	0xc0
+#define D18F1_IO_BASE1_LO	0xc8
+#define D18F1_IO_BASE2_LO	0xd0
+#define D18F1_IO_BASE3_LO	0xd8
+#define D18F1_MMIO_BASE7_LO	0xb8
+#define D18F1_MMIO_BASELIM0_HI	0x180
+#define D18F1_MMIO_BASE8_LO	0x1a0
+#define D18F1_MMIO_LIMIT8_LO	0x1a4
+#define D18F1_MMIO_BASE11_LO	0x1b8
+#define D18F1_MMIO_BASELIM8_HI	0x1c0
+#define NB_MMIO_BASE_LO(reg)	((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
+					? D18F1_MMIO_BASE0_LO \
+					: D18F1_MMIO_BASE8_LO \
+						- 8 * sizeof(uint64_t)))
+#define NB_MMIO_LIMIT_LO(reg)	(NB_MMIO_BASE_LO(reg) + sizeof(uint32_t))
+#define NB_MMIO_BASELIM_HI(reg)	((reg) * sizeof(uint32_t) + (((reg) < 8) \
+					? D18F1_MMIO_BASELIM0_HI \
+					: D18F1_MMIO_BASELIM8_HI \
+						- 8 * sizeof(uint32_t)))
+/* I/O base and limit */
+#define D18F1_IO_BASE0		0xc0
+# define IO_WE			(1 << 1)
+# define IO_RE			(1 << 0)
+#define D18F1_IO_LIMIT0		0xc4
+#define NB_IO_BASE(reg)		((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0)
+#define NB_IO_LIMIT(reg)	(NB_IO_BASE(reg) + sizeof(uint32_t))
+
+#define D18F1_DRAM_HOLE		0xf0
+# define DRAM_HOIST_VALID	(1 << 1)
+# define DRAM_HOLE_VALID	(1 << 0)
+#define D18F1_VGAEN		0xf4
+# define VGA_ADDR_ENABLE	(1 << 0)
+
+/* D18F5 */
+#define NB_CAPABILITIES2	0x84
+#define   CMP_CAP_MASK		0xff
+
+enum {
+	/* SMM handler area. */
+	SMM_SUBREGION_HANDLER,
+	/* SMM cache region. */
+	SMM_SUBREGION_CACHE,
+	/* Chipset specific area. */
+	SMM_SUBREGION_CHIPSET,
+	/* Total sub regions supported. */
+	SMM_SUBREGION_NUM,
+};
+
+/*
+ * Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG.
+ */
+void smm_region_info(void **start, size_t *size);
+/*
+ * Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on success, < 0 on failure.
+ */
+int smm_subregion(int sub, void **start, size_t *size);
+void domain_enable_resources(struct device *dev);
+void domain_set_resources(struct device *dev);
+void fam15_finalize(void *chip_info);
+uint32_t nb_ioapic_read(unsigned int index);
+void nb_ioapic_write(unsigned int index, uint32_t value);
+void *get_ap_entry_ptr(void);
+void set_ap_entry_ptr(void *entry);
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
+
+#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
new file mode 100644
index 0000000000..08d46973c0
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef __SOC_STONEYRIDGE_NVS_H__
+#define __SOC_STONEYRIDGE_NVS_H__
+
+#include <commonlib/helpers.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <soc/southbridge.h>
+
+typedef struct global_nvs_t {
+	/* Miscellaneous */
+	uint8_t		pcnt; /* 0x00 - Processor Count */
+	uint8_t		ppcm; /* 0x01 - Max PPC State */
+	uint8_t		lids; /* 0x02 - LID State */
+	uint8_t		pwrs; /* 0x03 - AC Power State */
+	uint8_t		dpte; /* 0x04 - Enable DPTF */
+	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
+	uint32_t	nhll; /* 0x21 - 0x24 - NHLT Length */
+	uint32_t	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	uint8_t		scdp; /* 0x29 - SD_CD GPIO portid */
+	uint8_t		scdo; /* 0x2A - GPIO pad relative offset */
+	uint8_t		tmps; /* 0x2B - Temperature Sensor ID */
+	uint8_t		tlvl; /* 0x2C - Throttle Level Limit */
+	uint8_t		flvl; /* 0x2D - Current FAN Level */
+	uint8_t		tcrt; /* 0x2E - Critical Threshold */
+	uint8_t		tpsv; /* 0x2F - Passive Threshold */
+	uint8_t		tmax; /* 0x30 - CPU Tj_max */
+	uint8_t		pad1[3];
+	aoac_devs_t	aoac; /* 0x34 - AOAC device enables */
+	uint16_t	fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */
+	uint16_t	fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */
+	uint32_t	fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */
+	uint32_t	fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */
+	uint32_t	eh10; /* 0x40 - EHCI BAR */
+	uint8_t		unused[184];
+
+	/* ChromeOS specific (0x100 - 0xfff) */
+	chromeos_acpi_t chromeos;
+} __packed global_nvs_t;
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+
+#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
new file mode 100644
index 0000000000..02fed7ab1e
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
+#define __PI_STONEYRIDGE_PCI_DEVS_H__
+
+#include <device/pci_def.h>
+
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define _SOC_DEV(slot, func)	pcidev_on_root(slot, func)
+#else
+#define _SOC_DEV(slot, func)	PCI_DEV(0, slot, func)
+#endif
+
+/* GNB Root Complex */
+#define GNB_DEV			0x0
+#define GNB_FUNC		0
+#define GNB_DEVID		0x1576
+#define GNB_DEVFN		PCI_DEVFN(GNB_DEV, GNB_FUNC)
+#define SOC_GNB_DEV		_SOC_DEV(GNB_DEV, GNB_FUNC)
+
+/* IOMMU */
+#define IOMMU_DEV		0x0
+#define IOMMU_FUNC		2
+#define IOMMU_DEVID		0x1577
+#define IOMMU_DEVFN		PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
+#define SOC_IOMMU_DEV		_SOC_DEV(IOMMU_DEV, IOMMU_FUNC)
+
+/* Internal Graphics */
+#define GFX_DEV			0x1
+#define GFX_FUNC		0
+#define GFX_DEVID		0x98e4 /* subject to SKU/OPN variation */
+#define GFX_DEVFN		PCI_DEVFN(GFX_DEV, GFX_FUNC)
+#define SOC_GFX_DEV		_SOC_DEV(GFX_DEV, GFX_FUNC)
+
+/* HD Audio 0 */
+#define HDA0_DEV		0x1
+#define HDA0_FUNC		1
+#define HDA0_DEVID		0x15b3
+#define HDA0_DEVFN		PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
+#define SOC_HDA0_DEV		_SOC_DEV(HDA0_DEV, HDA0_FUNC)
+
+/* Host Bridge */
+#define HOST_DEV		0x2
+#define HOST_FUNC		0
+#define HOST_DEVID		0x157b
+#define HOST_DEVFN		PCI_DEVFN(HOST_DEV, HOST_FUNC)
+#define SOC_HOST_DEV		_SOC_DEV(HOST_DEV, HOST_FUNC)
+
+/* PCIe GPP Bridge 0 */
+#define PCIE0_DEV		0x2
+#define PCIE0_FUNC		1
+#define PCIE0_DEVID		0x157c
+#define PCIE0_DEVFN		PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
+#define SOC_PCIE0_DEV		_SOC_DEV(PCIE0_DEV, PCIE0_FUNC)
+
+/* PCIe GPP Bridge 1 */
+#define PCIE1_DEV		0x2
+#define PCIE1_FUNC		2
+#define PCIE1_DEVID		0x157c
+#define PCIE1_DEVFN		PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
+#define SOC_PCIE1_DEV		_SOC_DEV(PCIE1_DEV, PCIE1_FUNC)
+
+/* PCIe GPP Bridge 2 */
+#define PCIE2_DEV		0x2
+#define PCIE2_FUNC		3
+#define PCIE2_DEVID		0x157c
+#define PCIE2_DEVFN		PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
+#define SOC_PCIE2_DEV		_SOC_DEV(PCIE2_DEV, PCIE2_FUNC)
+
+/* PCIe GPP Bridge 3 */
+#define PCIE3_DEV		0x2
+#define PCIE3_FUNC		4
+#define PCIE3_DEVID		0x157c
+#define PCIE3_DEVFN		PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
+#define SOC_PCIE3_DEV		_SOC_DEV(PCIE3_DEV, PCIE3_FUNC)
+
+/* PCIe GPP Bridge 4 */
+#define PCIE4_DEV		0x2
+#define PCIE4_FUNC		5
+#define PCIE4_DEVID		0x157c
+#define PCIE4_DEVFN		PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
+#define SOC_PCIE4_DEV		_SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
+
+/* Platform Security Processor */
+#define PSP_DEV			0x8
+#define PSP_FUNC		0
+#define PSP_DEVID		0x1578
+#define PSP_DEVFN		PCI_DEVFN(PSP_DEV, PSP_FUNC)
+#define SOC_PSP_DEV		_SOC_DEV(PSP_DEV, PSP_FUNC)
+
+/* HD Audio 1 */
+#define HDA1_DEV		0x9
+#define HDA1_FUNC		2
+#define HDA1_DEVID		0x157a
+#define HDA1_DEVFN		PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
+#define SOC_HDA1_DEV		_SOC_DEV(HDA1_DEV, HDA1_FUNC)
+
+/* HT Configuration */
+#define HT_DEV			0x18
+#define HT_FUNC			0
+#define HT_DEVID		0x15b0
+#define HT_DEVFN		PCI_DEVFN(HT_DEV, HT_FUNC)
+#define SOC_HT_DEV		_SOC_DEV(HT_DEV, HT_FUNC)
+
+/* Address Maps */
+#define ADDR_DEV		0x18
+#define ADDR_FUNC		1
+#define ADDR_DEVID		0x15b1
+#define ADDR_DEVFN		PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
+#define SOC_ADDR_DEV		_SOC_DEV(ADDR_DEV, ADDR_FUNC)
+
+/* DRAM Configuration */
+#define DCT_DEV			0x18
+#define DCT_FUNC		2
+#define DCT_DEVID		0x15b2
+#define DCT_DEVFN		PCI_DEVFN(DCT_DEV, DCT_FUNC)
+#define SOC_DCT_DEV		_SOC_DEV(DCT_DEV, DCT_FUNC)
+
+/* Misc. Configuration */
+#define MISC_DEV		0x18
+#define MISC_FUNC		3
+#define MISC_DEVID		0x15b3
+#define MISC_DEVFN		PCI_DEVFN(MISC_DEV, MISC_FUNC)
+#define SOC_MISC_DEV		_SOC_DEV(MISC_DEV, MISC_FUNC)
+
+/* PM Configuration */
+#define PM_DEV			0x18
+#define PM_FUNC			4
+#define PM_DEVID		0x15b4
+#define PM_DEVFN		PCI_DEVFN(PM_DEV, PM_FUNC)
+#define SOC_PM_DEV		_SOC_DEV(PM_DEV, PM_FUNC)
+
+/* Northbridge Configuration */
+#define NB_DEV			0x18
+#define NB_FUNC			5
+#define NB_DEVID		0x15b5
+#define NB_DEVFN		PCI_DEVFN(NB_DEV, NB_FUNC)
+#define SOC_NB_DEV		_SOC_DEV(NB_DEV, NB_FUNC)
+
+/* XHCI */
+#define XHCI_DEV		0x10
+#define XHCI_FUNC		0
+#define XHCI_DEVID		0x7914
+#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
+#define SOC_XHCI_DEV		_SOC_DEV(XHCI_DEV, XHCI_FUNC)
+
+/* SATA */
+#define SATA_DEV		0x11
+#define SATA_FUNC		0
+#define SATA_IDE_DEVID		0x7900
+#define AHCI_DEVID_MS		0x7901
+#define AHCI_DEVID_AMD		0x7904
+#define SATA_DEVFN		PCI_DEVFN(SATA_DEV, SATA_FUNC)
+#define SOC_SATA_DEV		_SOC_DEV(SATA_DEV, SATA_FUNC)
+
+/* EHCI */
+#define EHCI_DEV		0x12
+#define EHCI_FUNC		0
+#define EHCI_DEVID		0x7908
+#define EHCI1_DEVFN		PCI_DEVFN(EHCI_DEV, EHCI_FUNC)
+#define SOC_EHCI1_DEV		_SOC_DEV(EHCI_DEV, EHCI_FUNC)
+
+/* SMBUS */
+#define SMBUS_DEV		0x14
+#define SMBUS_FUNC		0
+#define SMBUS_DEVID		0x790b
+#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
+#define SOC_SMBUS_DEV		_SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
+
+/* LPC BUS */
+#define PCU_DEV			0x14
+#define LPC_FUNC		3
+#define LPC_DEVID		0x790e
+#define LPC_DEVFN		PCI_DEVFN(PCU_DEV, LPC_FUNC)
+#define SOC_LPC_DEV		_SOC_DEV(PCU_DEV, LPC_FUNC)
+
+/* SD Controller */
+#define SD_DEV			0x14
+#define SD_FUNC			7
+#define SD_DEVID		0x7906
+#define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
+#define SOC_SD_DEV		_SOC_DEV(SD_DEV, SD_FUNC)
+
+#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h
new file mode 100644
index 0000000000..6ce79b424e
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/romstage.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_ROMSTAGE_H__
+#define __STONEYRIDGE_ROMSTAGE_H__
+
+void mainboard_romstage_entry(int s3_resume);
+
+#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h
new file mode 100644
index 0000000000..391084d807
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/smbus.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_SMBUS_H__
+#define __STONEYRIDGE_SMBUS_H__
+
+#include <stdint.h>
+#include <soc/iomap.h>
+
+#define SMB_SPEED_400KHZ		(66000000 / (400000 * 4))
+
+/*
+ * Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100 * 1000 * 10)
+
+int do_smbus_read_byte(u32 mmio, u8 device, u8 address);
+int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val);
+int do_smbus_recv_byte(u32 mmio, u8 device);
+int do_smbus_send_byte(u32 mmio, u8 device, u8 val);
+
+#endif /* __STONEYRIDGE_SMBUS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
new file mode 100644
index 0000000000..000eed8554
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+
+
+#define SMI_GEVENTS			24
+#define SCIMAPS				58
+#define SCI_GPES			32
+
+#define SMI_EVENT_STATUS		0x0
+#define SMI_EVENT_ENABLE		0x04
+#define SMI_SCI_TRIG			0x08
+#define SMI_SCI_LEVEL			0x0c
+#define SMI_SCI_STATUS			0x10
+#define SMI_SCI_EN			0x14
+#define SMI_SCI_MAP0			0x40
+# define SMI_SCI_MAP(X)			(SMI_SCI_MAP0 + (X))
+
+/* SMI source and status */
+#define SMITYPE_AGPIO65				0
+#define SMITYPE_AGPIO66				1
+#define SMITYPE_AGPIO3				2
+#define SMITYPE_LPCPME_AGPIO22			3
+#define SMITYPE_GPIO4				4
+#define SMITYPE_LPCPD_AGPIOG21			5
+#define SMITYPE_IRTX1_G15			6
+#define SMITYPE_AGPIO5_DEVSLP0			7
+#define SMITYPE_WAKE_AGPIO2			8
+#define SMITYPE_APIO68_SGPIOCLK			9
+#define SMITYPE_AGPIO6				10
+#define SMITYPE_GPIO7				11
+#define SMITYPE_USBOC0_TRST_AGPIO16		12
+#define SMITYPE_USB0C1_TDI_AGPIO17		13
+#define SMITYPE_USBOC2_TCK_AGPIO18		14
+#define SMITYPE_TDO_USB0C3_AGPIO24		15
+#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23	16
+/* 17 Reserved */
+#define SMITYPE_BLINK_AGPIO11_USBOC7		18
+#define SMITYPE_SYSRESET_AGPIO1			19
+#define SMITYPE_IRRX1_AGPIO15			20
+#define SMITYPE_IRTX0_USBOC5_AGPIO13		21
+#define SMITYPE_GPIO9_SERPORTRX			22
+#define SMITYPE_GPIO8_SEPORTTX			23
+#define GEVENT_MASK ((1 << SMITYPE_AGPIO65)				\
+			| (1 << SMITYPE_AGPIO66)			\
+			| (1 << SMITYPE_AGPIO3)				\
+			| (1 << SMITYPE_LPCPME_AGPIO22)			\
+			| (1 << SMITYPE_GPIO4)				\
+			| (1 << SMITYPE_LPCPD_AGPIOG21)			\
+			| (1 << SMITYPE_IRTX1_G15)			\
+			| (1 << SMITYPE_AGPIO5_DEVSLP0)			\
+			| (1 << SMITYPE_WAKE_AGPIO2)			\
+			| (1 << SMITYPE_APIO68_SGPIOCLK)		\
+			| (1 << SMITYPE_AGPIO6)				\
+			| (1 << SMITYPE_GPIO7)				\
+			| (1 << SMITYPE_USBOC0_TRST_AGPIO16)		\
+			| (1 << SMITYPE_USB0C1_TDI_AGPIO17)		\
+			| (1 << SMITYPE_USBOC2_TCK_AGPIO18)		\
+			| (1 << SMITYPE_TDO_USB0C3_AGPIO24)		\
+			| (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23)	\
+			| (1 << SMITYPE_BLINK_AGPIO11_USBOC7)		\
+			| (1 << SMITYPE_SYSRESET_AGPIO1)		\
+			| (1 << SMITYPE_IRRX1_AGPIO15)			\
+			| (1 << SMITYPE_IRTX0_USBOC5_AGPIO13)		\
+			| (1 << SMITYPE_GPIO9_SERPORTRX))
+#define SMITYPE_EHCI0_WAKE			24
+#define SMITYPE_EHCI1_WAKE			25
+#define SMITYPE_ESPI_SYS			26
+#define SMITYPE_ESPI_WAKE_PME			27
+/* 28-32 Reserved */
+#define SMITYPE_FCH_FAKE0			33
+#define SMITYPE_FCH_FAKE1			34
+#define SMITYPE_FCH_FAKE2			35
+/* 36 Reserved */
+#define SMITYPE_SATA_GEVENT0			37
+#define SMITYPE_SATA_GEVENT1			38
+#define SMITYPE_ACP_WAKE			39
+#define SMITYPE_ECG				40
+#define SMITYPE_GPIO_CTL			41
+#define SMITYPE_CIR_PME				42
+#define SMITYPE_ALT_HPET_ALARM			43
+#define SMITYPE_FAN_THERMAL			44
+#define SMITYPE_ASF_MASTER_SLAVE		45
+#define SMITYPE_I2S_WAKE			46
+#define SMITYPE_SMBUS0_MASTER			47
+#define SMITYPE_TWARN				48
+#define SMITYPE_TRAFFIC_MON			49
+#define SMITYPE_ILLB				50
+#define SMITYPE_PWRBUTTON_UP			51
+#define SMITYPE_PROCHOT				52
+#define SMITYPE_APU_HW				53
+#define SMITYPE_NB_SCI				54
+#define SMITYPE_RAS_SERR			55
+#define SMITYPE_XHC0_PME			56
+/* 57 Reserved */
+#define SMITYPE_ACDC_TIMER			58
+/* 59-62 Reserved */
+#define SMITYPE_TEMP_TSI			63
+#define SMITYPE_KB_RESET			64
+#define SMITYPE_SLP_TYP				65
+#define SMITYPE_AL2H_ACPI			66
+#define SMITYPE_AHCI				67
+/* 68-71 Reserved */
+#define SMITYPE_GBL_RLS				72
+#define SMITYPE_BIOS_RLS			73
+#define SMITYPE_PWRBUTTON_DOWN			74
+#define SMITYPE_SMI_CMD_PORT			75
+#define SMITYPE_USB_SMI				76
+#define SMITYPE_SERIRQ				77
+#define SMITYPE_SMBUS0_INTR			78
+#define SMITYPE_XHC_ERROR			80
+#define SMITYPE_INTRUDER			81
+#define SMITYPE_VBAT_LOW			82
+#define SMITYPE_PROTHOT				83
+#define SMITYPE_PCI_SERR			84
+#define SMITYPE_GPP_SERR			85
+/* 85-88 Reserved */
+#define SMITYPE_TMERTRIP			89
+#define SMITYPE_EMUL60_64			90
+#define SMITYPE_USB_FLR				91
+#define SMITYPE_SATA_FLR			92
+#define SMITYPE_AZ_FLR				93
+/* 94-132 Reserved */
+#define SMITYPE_FANIN0				133
+/* 134-137 Reserved */
+#define SMITYPE_FAKE0				138
+#define SMITYPE_FAKE1				139
+#define SMITYPE_FAKE2				140
+/* 141 Reserved */
+#define SMITYPE_SHORT_TIMER			142
+#define SMITYPE_LONG_TIMER			143
+#define SMITYPE_AB_SMI				144
+#define SMITYPE_SOFT_RESET			145
+/* 146-147 Reserved */
+#define SMITYPE_IOTRAP0				148
+/* 149-151 Reserved */
+#define SMITYPE_MEMTRAP0			152
+/* 153-155 Reserved */
+#define SMITYPE_CFGTRAP0			156
+/* 157-159 Reserved */
+#define NUMBER_SMITYPES				160
+#define TYPE_TO_MASK(X)				(1 << (X) % 32)
+
+#define SMI_REG_SMISTS0			0x80
+#define SMI_REG_SMISTS1			0x84
+#define SMI_REG_SMISTS2			0x88
+#define SMI_REG_SMISTS3			0x8c
+#define SMI_REG_SMISTS4			0x90
+
+#define SMI_REG_POINTER			0x94
+# define SMI_STATUS_SRC_SCI			(1 << 0)
+# define SMI_STATUS_SRC_0			(1 << 1) /* SMIx80 */
+# define SMI_STATUS_SRC_1			(1 << 2) /* SMIx84... */
+# define SMI_STATUS_SRC_2			(1 << 3)
+# define SMI_STATUS_SRC_3			(1 << 4)
+# define SMI_STATUS_SRC_4			(1 << 5)
+
+#define SMI_TIMER			0x96
+#define SMI_TIMER_MASK				0x7fff
+#define SMI_TIMER_EN				(1 << 15)
+
+#define SMI_REG_SMITRIG0		0x98
+# define SMITRG0_EOS				(1 << 28)
+# define SMI_TIMER_SEL				(1 << 29)
+# define SMITRG0_SMIENB				(1 << 31)
+
+#define SMI_REG_CONTROL0		0xa0
+#define SMI_REG_CONTROL1		0xa4
+#define SMI_REG_CONTROL2		0xa8
+#define SMI_REG_CONTROL3		0xac
+#define SMI_REG_CONTROL4		0xb0
+#define SMI_REG_CONTROL5		0xb4
+#define SMI_REG_CONTROL6		0xb8
+#define SMI_REG_CONTROL7		0xbc
+#define SMI_REG_CONTROL8		0xc0
+#define SMI_REG_CONTROL9		0xc4
+
+enum smi_mode {
+	SMI_MODE_DISABLE = 0,
+	SMI_MODE_SMI = 1,
+	SMI_MODE_NMI = 2,
+	SMI_MODE_IRQ13 = 3,
+};
+
+enum smi_sci_type {
+	INTERRUPT_NONE,
+	INTERRUPT_SCI,
+	INTERRUPT_SMI,
+	INTERRUPT_BOTH,
+};
+
+enum smi_sci_lvl {
+	SMI_SCI_LVL_LOW,
+	SMI_SCI_LVL_HIGH,
+};
+
+enum smi_sci_dir {
+	SMI_SCI_EDG,
+	SMI_SCI_LVL,
+};
+
+struct smi_sources_t {
+	int type;
+	void (*handler)(void);
+};
+
+struct sci_source {
+	uint8_t scimap;		/* SCIMAP 0-57 */
+	uint8_t gpe;		/* 32 GPEs */
+	uint8_t direction;	/* Active High or Low,  smi_sci_lvl */
+	uint8_t level;		/* Edge or Level,  smi_sci_dir */
+};
+
+uint16_t pm_acpi_smi_cmd_port(void);
+void configure_smi(uint8_t smi_num, uint8_t mode);
+void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
+void configure_scimap(const struct sci_source *sci);
+void disable_gevent_smi(uint8_t gevent);
+void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
+void soc_route_sci(uint8_t event);
+
+#ifndef __SMM__
+void enable_smi_generation(void);
+#endif
+
+#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
new file mode 100644
index 0000000000..ad4040759c
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -0,0 +1,415 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010-2017 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_H__
+#define __STONEYRIDGE_H__
+
+#include <types.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <soc/iomap.h>
+#include "chip.h"
+
+/*
+ * AcpiMmio Region
+ *  - fixed addresses offset from 0xfed80000
+ */
+
+/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PM_DECODE_EN			0x00
+#define   CF9_IO_EN			BIT(1)
+#define   LEGACY_IO_EN			BIT(0)
+#define PM_ISA_CONTROL			0x04
+#define   MMIO_EN			BIT(1)
+#define PM_PCI_CTRL			0x08
+#define   FORCE_SLPSTATE_RETRY		BIT(25)
+#define   FORCE_STPCLK_RETRY		BIT(24)
+
+#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN */
+
+#define PWR_RESET_CFG			0x10
+#define   TOGGLE_ALL_PWR_GOOD		BIT(1)
+
+#define PM_SERIRQ_CONF			0x54
+#define   PM_SERIRQ_NUM_BITS_17		0x0000
+#define   PM_SERIRQ_NUM_BITS_18		0x0004
+#define   PM_SERIRQ_NUM_BITS_19		0x0008
+#define   PM_SERIRQ_NUM_BITS_20		0x000c
+#define   PM_SERIRQ_NUM_BITS_21		0x0010
+#define   PM_SERIRQ_NUM_BITS_22		0x0014
+#define   PM_SERIRQ_NUM_BITS_23		0x0018
+#define   PM_SERIRQ_NUM_BITS_24		0x001c
+#define   PM_SERIRQ_MODE		BIT(6)
+#define   PM_SERIRQ_ENABLE		BIT(7)
+
+#define PM_RTC_SHADOW			0x5b	/* state when power resumes */
+#define   PM_S5_AT_POWER_RECOVERY	0x04	/* S5 */
+#define   PM_RESTORE_S0_IF_PREV_S0	0x07	/* S0 if previously at S0 */
+
+#define PM_EVT_BLK			0x60
+#define   WAK_STS			BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
+#define   PCIEXPWAK_STS			BIT(14)
+#define   RTC_STS			BIT(10)
+#define   PWRBTN_STS			BIT(8)
+#define   GBL_STS			BIT(5)
+#define   BM_STS			BIT(4)
+#define   TIMER_STS			BIT(0)
+#define   PCIEXPWAK_DIS			BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
+#define   RTC_EN			BIT(10)
+#define   PWRBTN_EN			BIT(8)
+#define   GBL_EN			BIT(5)
+#define   TIMER_STS			BIT(0)
+#define PM1_CNT_BLK			0x62
+#define PM_TMR_BLK			0x64
+#define PM_CPU_CTRL			0x66
+#define PM_GPE0_BLK			0x68
+#define PM_ACPI_SMI_CMD			0x6a
+#define PM_ACPI_CONF			0x74
+#define   PM_ACPI_DECODE_STD		BIT(0)
+#define   PM_ACPI_GLOBAL_EN		BIT(1)
+#define   PM_ACPI_RTC_EN_EN		BIT(2)
+#define   PM_ACPI_TIMER_EN_EN		BIT(4)
+#define   PM_ACPI_MASK_ARB_DIS		BIT(6)
+#define   PM_ACPI_BIOS_RLS		BIT(7)
+#define   PM_ACPI_PWRBTNEN_EN		BIT(8)
+#define   PM_ACPI_REDUCED_HW_EN		BIT(9)
+#define   PM_ACPI_BLOCK_PCIE_PME	BIT(24)
+#define   PM_ACPI_PCIE_WAK_MASK		BIT(25)
+#define   PM_ACPI_WAKE_AS_GEVENT	BIT(27)
+#define   PM_ACPI_NB_PME_GEVENT		BIT(28)
+#define   PM_ACPI_RTC_WAKE_EN		BIT(29)
+#define PM_RST_CTRL1			0xbe
+#define   SLPTYPE_CONTROL_EN		BIT(5)
+#define PM_RST_STATUS			0xc0
+#define PM_PCIB_CFG			0xea
+#define   PM_GENINT_DISABLE		BIT(0)
+#define PM_LPC_GATING			0xec
+#define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
+#define   PM_LPC_A20_EN			BIT(1)
+#define   PM_LPC_ENABLE			BIT(0)
+#define PM_USB_ENABLE			0xef
+#define   PM_USB_ALL_CONTROLLERS	0x7f
+
+/* SMBUS MMIO offsets 0xfed80a00 */
+#define SMBHSTSTAT			0x0
+#define   SMBHST_STAT_FAILED		0x10
+#define   SMBHST_STAT_COLLISION		0x08
+#define   SMBHST_STAT_ERROR		0x04
+#define   SMBHST_STAT_INTERRUPT		0x02
+#define   SMBHST_STAT_BUSY		0x01
+#define   SMBHST_STAT_CLEAR		0xff
+#define   SMBHST_STAT_NOERROR		0x02
+#define   SMBHST_STAT_VAL_BITS		0x1f
+#define   SMBHST_STAT_ERROR_BITS	0x1c
+
+#define SMBSLVSTAT			0x1
+#define   SMBSLV_STAT_ALERT		0x20
+#define   SMBSLV_STAT_SHADOW2		0x10
+#define   SMBSLV_STAT_SHADOW1		0x08
+#define   SMBSLV_STAT_SLV_STS		0x04
+#define   SMBSLV_STAT_SLV_INIT		0x02
+#define   SMBSLV_STAT_SLV_BUSY		0x01
+#define   SMBSLV_STAT_CLEAR		0x1f
+
+#define SMBHSTCTRL			0x2
+#define   SMBHST_CTRL_RST		0x80
+#define   SMBHST_CTRL_STRT		0x40
+#define   SMBHST_CTRL_QCK_RW		0x00
+#define   SMBHST_CTRL_BTE_RW		0x04
+#define   SMBHST_CTRL_BDT_RW		0x08
+#define   SMBHST_CTRL_WDT_RW		0x0c
+#define   SMBHST_CTRL_BLK_RW		0x14
+#define   SMBHST_CTRL_MODE_BITS		0x1c
+#define   SMBHST_CTRL_KILL		0x02
+#define   SMBHST_CTRL_IEN		0x01
+
+#define SMBHSTCMD			0x3
+#define SMBHSTADDR			0x4
+#define SMBHSTDAT0			0x5
+#define SMBHSTDAT1			0x6
+#define SMBHSTBLKDAT			0x7
+#define SMBSLVCTRL			0x8
+#define SMBSLVCMD_SHADOW		0x9
+#define SMBSLVEVT			0xa
+#define SMBSLVDAT			0xc
+#define SMBTIMING			0xe
+
+/* FCH MISC Registers 0xfed80e00 */
+#define GPP_CLK_CNTRL			0x00
+#define   GPP_CLK2_REQ_MAP_SHIFT	8
+#define   GPP_CLK2_REQ_MAP_MASK		(0xf << GPP_CLK2_REQ_MAP_SHIFT)
+#define   GPP_CLK2_REQ_MAP_CLK_REQ2	3
+#define   GPP_CLK0_REQ_MAP_SHIFT	0
+#define   GPP_CLK0_REQ_MAP_MASK		(0xf << GPP_CLK0_REQ_MAP_SHIFT)
+#define   GPP_CLK0_REQ_MAP_CLK_REQ0	1
+#define MISC_CGPLL_CONFIG1		0x08
+#define   CG1PLL_SPREAD_SPECTRUM_ENABLE	BIT(0)
+#define MISC_CGPLL_CONFIG3		0x10
+#define   CG1PLL_REFDIV_SHIFT		0
+#define   CG1PLL_REFDIV_MASK		(0x3ff << CG1PLL_REFDIV_SHIFT)
+#define   CG1PLL_FBDIV_SHIFT		10
+#define   CG1PLL_FBDIV_MASK		(0xfff << CG1PLL_FBDIV_SHIFT)
+#define MISC_CGPLL_CONFIG4		0x14
+#define   SS_STEP_SIZE_DSFRAC_SHIFT	0
+#define   SS_STEP_SIZE_DSFRAC_MASK	(0xffff << SS_STEP_SIZE_DSFRAC_SHIFT)
+#define   SS_AMOUNT_DSFRAC_SHIFT	16
+#define   SS_AMOUNT_DSFRAC_MASK		(0xffff << SS_AMOUNT_DSFRAC_SHIFT)
+#define MISC_CGPLL_CONFIG5		0x18
+#define   SS_AMOUNT_NFRAC_SLIP_SHIFT	8
+#define   SS_AMOUNT_NFRAC_SLIP_MASK	(0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6		0x1c
+#define   CG1PLL_LF_MODE_SHIFT		9
+#define   CG1PLL_LF_MODE_MASK		(0x1ff << CG1PLL_LF_MODE_SHIFT)
+#define MISC_CLK_CNTL1			0x40
+#define   CG1PLL_FBDIV_TEST		BIT(26)
+#define   OSCOUT1_CLK_OUTPUT_ENB	BIT(2)  /* 0 = Enabled, 1 = Disabled */
+#define   OSCOUT2_CLK_OUTPUT_ENB	BIT(7)  /* 0 = Enabled, 1 = Disabled */
+
+/* XHCI_PM Registers:  0xfed81c00 */
+#define XHCI_PM_INDIRECT_INDEX		0x48
+#define XHCI_PM_INDIRECT_DATA		0x4c
+#define   XHCI_OVER_CURRENT_CONTROL	0x30
+#define     USB_OC0			0
+#define     USB_OC1			1
+#define     USB_OC2			2
+#define     USB_OC3			3
+#define     USB_OC4			4
+#define     USB_OC5			5
+#define     USB_OC6			6
+#define     USB_OC7			7
+#define     USB_OC_DISABLE		0xf
+#define     USB_OC_DISABLE_ALL		0xffff
+#define     OC_PORT0_SHIFT		0
+#define     OC_PORT1_SHIFT		4
+#define     OC_PORT2_SHIFT		8
+#define     OC_PORT3_SHIFT		12
+
+#define EHCI_OVER_CURRENT_CONTROL	0x70
+#define EHCI_HUB_CONFIG4		0x90
+#define   DEBUG_PORT_SELECT_SHIFT	  16
+#define   DEBUG_PORT_ENABLE		  BIT(18)
+#define   DEBUG_PORT_MASK		(BIT(16) | BIT(17) | BIT(18))
+
+/* FCH AOAC Registers 0xfed81e00 */
+#define FCH_AOAC_D3_CONTROL_CLK_GEN	0x40
+#define FCH_AOAC_D3_CONTROL_I2C0	0x4a
+#define FCH_AOAC_D3_CONTROL_I2C1	0x4c
+#define FCH_AOAC_D3_CONTROL_I2C2	0x4e
+#define FCH_AOAC_D3_CONTROL_I2C3	0x50
+#define FCH_AOAC_D3_CONTROL_UART0	0x56
+#define FCH_AOAC_D3_CONTROL_UART1	0x58
+#define FCH_AOAC_D3_CONTROL_AMBA	0x62
+#define FCH_AOAC_D3_CONTROL_USB2	0x64
+#define FCH_AOAC_D3_CONTROL_USB3	0x6e
+/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
+#define   FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
+#define   FCH_AOAC_DEVICE_STATE		BIT(2)
+#define   FCH_AOAC_PWR_ON_DEV		BIT(3)
+#define   FCH_AOAC_SW_PWR_ON_RSTB	BIT(4)
+#define   FCH_AOAC_SW_REF_CLK_OK	BIT(5)
+#define   FCH_AOAC_SW_RST_B		BIT(6)
+#define   FCH_AOAC_IS_SW_CONTROL	BIT(7)
+
+#define FCH_AOAC_D3_STATE_CLK_GEN	0x41
+#define FCH_AOAC_D3_STATE_I2C0		0x4b
+#define FCH_AOAC_D3_STATE_I2C1		0x4d
+#define FCH_AOAC_D3_STATE_I2C2		0x4f
+#define FCH_AOAC_D3_STATE_I2C3		0x51
+#define FCH_AOAC_D3_STATE_UART0		0x57
+#define FCH_AOAC_D3_STATE_UART1		0x59
+#define FCH_AOAC_D3_STATE_AMBA		0x63
+#define FCH_AOAC_D3_STATE_USB2		0x65
+#define FCH_AOAC_D3_STATE_USB3		0x6f
+/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
+#define   FCH_AOAC_PWR_RST_STATE	BIT(0)
+#define   FCH_AOAC_RST_CLK_OK_STATE	BIT(1)
+#define   FCH_AOAC_RST_B_STATE		BIT(2)
+#define   FCH_AOAC_DEV_OFF_GATING_STATE	BIT(3)
+#define   FCH_AOAC_D3COLD		BIT(4)
+#define   FCH_AOAC_CLK_OK_STATE		BIT(5)
+#define   FCH_AOAC_STAT0		BIT(6)
+#define   FCH_AOAC_STAT1		BIT(7)
+
+#define PM1_LIMIT			16
+#define GPE0_LIMIT			28
+#define TOTAL_BITS(a)			(8 * sizeof(a))
+
+/* SATA Controller D11F0 */
+#define SATA_MISC_CONTROL_REG		0x40
+#define SATA_MISC_SUBCLASS_WREN		BIT(0)
+/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */
+#define SATA_CAPABILITIES_REG		0xfc
+#define SATA_CAPABILITY_SPM		BIT(12)
+
+/* SPI Controller (base address in D14F3xA0) */
+#define SPI_BASE_ALIGNMENT		BIT(6)
+
+#define SPI_CNTRL0			0x00
+#define   SPI_BUSY			BIT(31)
+#define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
+/* Nominal is 16.7MHz on older devices, 33MHz on newer */
+#define   SPI_READ_MODE_NOM		0x00000000
+#define   SPI_READ_MODE_DUAL112		(          BIT(29)          )
+#define   SPI_READ_MODE_QUAD114		(          BIT(29) | BIT(18))
+#define   SPI_READ_MODE_DUAL122		(BIT(30)                    )
+#define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
+#define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
+#define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
+#define   SPI_FIFO_PTR_CLR		BIT(20)
+#define   SPI_ARB_ENABLE		BIT(19)
+#define   EXEC_OPCODE			BIT(16)
+#define SPI_CNTRL1			0x0c
+#define SPI_CMD_CODE			0x45
+#define SPI_CMD_TRIGGER			0x47
+#define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
+#define SPI_TX_BYTE_COUNT		0x48
+#define SPI_RX_BYTE_COUNT		0x4b
+#define SPI_STATUS			0x4c
+#define   SPI_DONE_BYTE_COUNT_SHIFT	0
+#define   SPI_DONE_BYTE_COUNT_MASK	0xff
+#define   SPI_FIFO_WR_PTR_SHIFT		8
+#define   SPI_FIFO_WR_PTR_MASK		0x7f
+#define   SPI_FIFO_RD_PTR_SHIFT		16
+#define   SPI_FIFO_RD_PTR_MASK		0x7f
+#define SPI_FIFO			0x80
+#define   SPI_FIFO_DEPTH		(0xc7 - SPI_FIFO)
+
+#define SPI100_ENABLE			0x20
+#define   SPI_USE_SPI100		BIT(0)
+
+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
+#define SPI100_SPEED_CONFIG		0x22
+#define   SPI_SPEED_66M			(0x0)
+#define   SPI_SPEED_33M			(                  BIT(0))
+#define   SPI_SPEED_22M			(         BIT(1)         )
+#define   SPI_SPEED_16M			(         BIT(1) | BIT(0))
+#define   SPI_SPEED_100M		(BIT(2)                  )
+#define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
+#define   SPI_NORM_SPEED_NEW_SH		12
+#define   SPI_FAST_SPEED_NEW_SH		8
+#define   SPI_ALT_SPEED_NEW_SH		4
+#define   SPI_TPM_SPEED_NEW_SH		0
+
+#define SPI100_HOST_PREF_CONFIG		0x2c
+#define   SPI_RD4DW_EN_HOST		BIT(15)
+
+/* Platform Security Processor D8F0 */
+#define PSP_MAILBOX_BAR			PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
+#define PSP_BAR_ENABLES			0x48
+#define  PSP_MAILBOX_BAR_EN		0x10
+
+/* IO 0xcf9 - Reset control port*/
+#define   FULL_RST			BIT(3)
+#define   RST_CMD			BIT(2)
+#define   SYS_RST			BIT(1)
+
+struct stoneyridge_aoac {
+	int enable;
+	int status;
+};
+
+typedef struct aoac_devs {
+	unsigned int :5;
+	unsigned int ic0e:1; /* 5: I2C0 */
+	unsigned int ic1e:1; /* 6: I2C1 */
+	unsigned int ic2e:1; /* 7: I2C2 */
+	unsigned int ic3e:1; /* 8: I2C3 */
+	unsigned int :2;
+	unsigned int ut0e:1; /* 11: UART0 */
+	unsigned int ut1e:1; /* 12: UART1 */
+	unsigned int :2;
+	unsigned int st_e:1; /* 15: SATA */
+	unsigned int :2;
+	unsigned int ehce:1; /* 18: EHCI */
+	unsigned int :4;
+	unsigned int xhce:1; /* 23: xHCI */
+	unsigned int sd_e:1; /* 24: SDIO */
+	unsigned int :2;
+	unsigned int espi:1; /* 27: ESPI */
+	unsigned int :4;
+} __packed aoac_devs_t;
+
+struct soc_power_reg {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t gpe0_sts;
+	uint32_t gpe0_en;
+	uint16_t wake_from;
+};
+
+#define XHCI_FW_SIG_OFFSET			0xc
+#define XHCI_FW_ADDR_OFFSET			0x6
+#define XHCI_FW_SIZE_OFFSET			0x8
+#define XHCI_FW_BOOTRAM_SIZE			0x8000
+
+void enable_aoac_devices(void);
+void sb_clk_output_48Mhz(u32 osc);
+void sb_disable_4dw_burst(void);
+void sb_enable(struct device *dev);
+void southbridge_final(void *chip_info);
+void southbridge_init(void *chip_info);
+void sb_read_mode(u32 mode);
+void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
+void bootblock_fch_early_init(void);
+void bootblock_fch_init(void);
+/**
+ * @brief Save the UMA bize returned by AGESA
+ *
+ * @param size = in bytes
+ *
+ * @return none
+ */
+void save_uma_size(uint32_t size);
+/**
+ * @brief Save the UMA base address returned by AGESA
+ *
+ * @param base = 64bit base address
+ *
+ * @return none
+ */
+void save_uma_base(uint64_t base);
+/**
+ * @brief Get the saved UMA size
+ *
+ * @param none
+ *
+ * @return size in bytes
+ */
+uint32_t get_uma_size(void);
+/**
+ * @brief Get the saved UMA base
+ *
+ * @param none
+ *
+ * @return 64bit base address
+ */
+uint64_t get_uma_base(void);
+/*
+ * Call the mainboard to get the USB Over Current Map. The mainboard
+ * returns the map and 0 on Success or -1 on error or no map. There is
+ * a default weak function in usb.c if the mainboard doesn't have any
+ * over current support.
+ */
+int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map);
+int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map);
+
+/* Initialize all the i2c buses that are marked with early init. */
+void i2c_soc_early_init(void);
+
+/* Initialize all the i2c buses that are not marked with early init. */
+void i2c_soc_init(void);
+
+#endif /* __STONEYRIDGE_H__ */