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authorFurquan Shaikh <furquan@google.com>2020-06-10 16:37:23 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-13 06:50:51 +0000
commitbc45650b5fba1da8214687aaef36b60a1fa19a6c (patch)
tree8d3096cdb77ddef8b609f37d6ed5ab3ef1ef7bd9 /src/soc/amd/picasso/memmap.c
parentc3bb6923bdcd20f4b343ba373a7d211655d6468a (diff)
downloadcoreboot-bc45650b5fba1da8214687aaef36b60a1fa19a6c.tar.xz
soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM
This change updates memlayout.ld for Picasso to place all early stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at the bottom of DRAM starting at 32MiB. This uses static allocation for most components by defining Kconfig variables for base and size. It relies on the linker to complain if any of the assumptions are broken. This also allows romstage to use linker symbols for _early_reserved_dram and _eearly_reserved_dram to store information in CBMEM about the early DRAM usage by coreboot before ramstage starts execution. This allows ramstage to reserve this memory region in BIOS tables so that S3 resume can reuse the same space without corrupting OS memory. BUG=b:155322763 TEST=Verified memory reported by coreboot: Writing coreboot table at 0xcc656000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000001ffffff: RAM 4. 0000000002000000-000000000223ffff: RESERVED 5. 0000000002240000-00000000cc512fff: RAM 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES 9. 00000000cd800000-00000000cfffffff: RESERVED 10. 00000000f8000000-00000000fbffffff: RESERVED 11. 0000000100000000-000000042f33ffff: RAM 12. 000000042f340000-000000042fffffff: RESERVED Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/memmap.c')
-rw-r--r--src/soc/amd/picasso/memmap.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 5f4ba42da1..42a330726e 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -4,12 +4,14 @@
#include <assert.h>
#include <stdint.h>
+#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
#include <memrange.h>
#include <fsp/util.h>
#include <FspGuids.h>
+#include <soc/memmap.h>
/*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach
@@ -57,3 +59,26 @@ void smm_region(uintptr_t *start, size_t *size)
once = 1;
}
}
+
+void memmap_stash_early_dram_usage(void)
+{
+ struct memmap_early_dram *e;
+
+ e = cbmem_add(CBMEM_ID_CB_EARLY_DRAM, sizeof(*e));
+
+ if (!e)
+ die("ERROR: Failed to stash early dram usage!\n");
+
+ e->base = (uint32_t)(uintptr_t)_early_reserved_dram;
+ e->size = REGION_SIZE(early_reserved_dram);
+}
+
+const struct memmap_early_dram *memmap_get_early_dram_usage(void)
+{
+ struct memmap_early_dram *e = cbmem_find(CBMEM_ID_CB_EARLY_DRAM);
+
+ if (!e)
+ die("ERROR: Failed to read early dram usage!\n");
+
+ return e;
+}