diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2020-06-26 08:47:00 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-24 22:01:51 +0000 |
| commit | ab83b43b34d729ad260d8f68b725ed025eaafb5e (patch) | |
| tree | 7c07485cc1d6bb1b264539d1e32e2786c21650a6 /src/soc/amd/picasso/southbridge.c | |
| parent | 9857c906854752848cbe0b68fb0c35e924a3dd28 (diff) | |
| download | coreboot-ab83b43b34d729ad260d8f68b725ed025eaafb5e.tar.xz | |
soc/amd/picasso/sb: Gate FCH AL2AHB clocks
Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.
BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/southbridge.c')
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index cb22195546..4cd24dd900 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -328,11 +328,29 @@ static void set_nvs_sws(void *unused) BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); +/* + * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks + * and unneeded for Raven/Picasso so gate them to save power. + */ +static void al2ahb_clock_gate(void) +{ + uint8_t al2ahb_val; + uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; + + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); + al2ahb_val |= AL2AHB_CLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); + al2ahb_val |= AL2AHB_HCLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); +} + void southbridge_init(void *chip_info) { i2c_soc_init(); sb_init_acpi_ports(); acpi_clear_pm1_status(); + al2ahb_clock_gate(); } static void set_sb_final_nvs(void) |