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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-02-19 15:52:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:42:14 +0000 |
| commit | ebb7f54b1a107816e4f83bc31f1631acb85700d1 (patch) | |
| tree | 3568e691490943cc111b5ad590e0b74194a86a51 /src/soc/amd/picasso/southbridge.c | |
| parent | 3180af7fd6a86d202c241b02afa9cc4c0b9d9262 (diff) | |
| download | coreboot-ebb7f54b1a107816e4f83bc31f1631acb85700d1.tar.xz | |
soc/intel/xeon_sp: Enable LPC generic IO decode range
To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.
Tested on OCP Tioga Pass with BMC LPC working.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/southbridge.c')
0 files changed, 0 insertions, 0 deletions