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authorFurquan Shaikh <furquan@google.com>2020-04-27 15:45:20 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-28 22:56:59 +0000
commit52f8926159917d87cc33c33183225be7eb470e0d (patch)
treeb07775b9a561cc7856eddcb32faea77673240b25 /src/soc/amd/picasso
parent088b9e337cfa0bce05ddbdbc643c29676e842f8f (diff)
downloadcoreboot-52f8926159917d87cc33c33183225be7eb470e0d.tar.xz
soc/amd/picasso: Use AMD common SATA driver
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl. BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT. Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/acpi/sb_pci0_fch.asl5
-rw-r--r--src/soc/amd/picasso/chip.c2
2 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 3e6029e0e0..04e72c0a45 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -23,11 +23,6 @@ Method(_OSC,4)
/* Describe the Southbridge devices */
-/* 0:11.0 - SATA */
-Device(STCR) {
- Name(_ADR, 0x00110000)
-} /* end STCR */
-
/* 0:14.0 - SMBUS */
Device(SBUS) {
Name(_ADR, 0x00140000)
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 4b25b888d6..201afb40dd 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -65,8 +65,6 @@ const char *soc_acpi_name(const struct device *dev)
return "AZHD";
case LPC_DEVFN:
return "LPCB";
- case SATA_DEVFN:
- return "STCR";
case SMBUS_DEVFN:
return "SBUS";
case XHCI0_DEVFN: