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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-11 12:18:20 -0600
committerMartin Roth <martinroth@google.com>2019-07-03 21:30:16 +0000
commitbc4c903c1f0bbf5297309082f31cfc2f70addb99 (patch)
tree99924f3d876aad0b7d56dfd974ece168c5028c9f /src/soc/amd/picasso
parent30cf1551683810504f7823e42d4cb6515459cff8 (diff)
downloadcoreboot-bc4c903c1f0bbf5297309082f31cfc2f70addb99.tar.xz
soc/amd/picasso: Change all remaining soc names
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/Kconfig34
-rw-r--r--src/soc/amd/picasso/Makefile.inc20
-rw-r--r--src/soc/amd/picasso/acpi.c4
-rw-r--r--src/soc/amd/picasso/chip.c10
-rw-r--r--src/soc/amd/picasso/chip.h8
-rw-r--r--src/soc/amd/picasso/cpu.c2
-rw-r--r--src/soc/amd/picasso/i2c.c10
-rw-r--r--src/soc/amd/picasso/include/soc/acpi.h2
-rw-r--r--src/soc/amd/picasso/include/soc/cpu.h2
-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h12
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h2
-rw-r--r--src/soc/amd/picasso/romstage.c4
-rw-r--r--src/soc/amd/picasso/southbridge.c20
13 files changed, 65 insertions, 65 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 382aaef96e..9e96c1e98a 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -185,9 +185,9 @@ config STONEYRIDGE_GEC_FWM_FILE
config AMD_PUBKEY_FILE
string "AMD public Key"
- default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin"
+ default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin"
-config STONEYRIDGE_SATA_MODE
+config PICASSO_SATA_MODE
int "SATA Mode"
default 0
range 0 6
@@ -203,33 +203,33 @@ config STONEYRIDGE_SATA_MODE
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
comment "NATIVE"
- depends on STONEYRIDGE_SATA_MODE = 0
+ depends on PICASSO_SATA_MODE = 0
comment "AHCI"
- depends on STONEYRIDGE_SATA_MODE = 2
+ depends on PICASSO_SATA_MODE = 2
comment "LEGACY IDE"
- depends on STONEYRIDGE_SATA_MODE = 3
+ depends on PICASSO_SATA_MODE = 3
comment "IDE to AHCI"
- depends on STONEYRIDGE_SATA_MODE = 4
+ depends on PICASSO_SATA_MODE = 4
comment "AHCI7804"
- depends on STONEYRIDGE_SATA_MODE = 5
+ depends on PICASSO_SATA_MODE = 5
comment "IDE to AHCI7804"
- depends on STONEYRIDGE_SATA_MODE = 6
+ depends on PICASSO_SATA_MODE = 6
-if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
+if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
config AHCI_ROM_ID
string "AHCI device PCI IDs"
- default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
- default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
+ default "1022,7801" if PICASSO_SATA_MODE = 2
+ default "1022,7804" if PICASSO_SATA_MODE = 5
-endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
+endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
-config STONEYRIDGE_LEGACY_FREE
+config PICASSO_LEGACY_FREE
bool "System is legacy free"
help
Select y if there is no keyboard controller in the system.
@@ -242,22 +242,22 @@ config SERIRQ_CONTINUOUS_MODE
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
-config STONEYRIDGE_ACPI_IO_BASE
+config PICASSO_ACPI_IO_BASE
hex
default 0x400
help
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
-config STONEYRIDGE_UART
- bool "UART controller on Stoney Ridge"
+config PICASSO_UART
+ bool "UART controller on Picasso"
default n
select DRIVERS_UART_8250MEM
select DRIVERS_UART_8250MEM_32
select NO_UART_ON_SUPERIO
select UART_OVERRIDE_REFCLK
help
- There are two UART controllers in Stoney Ridge.
+ There are two UART controllers in Picasso.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index e8c022fcda..b8a29c29a9 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -52,7 +52,7 @@ romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += smbus.c
romstage-y += ramtop.c
-romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+romstage-$(CONFIG_PICASSO_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
@@ -63,12 +63,12 @@ verstage-y += i2c.c
verstage-y += monotonic_timer.c
verstage-y += pmutil.c
verstage-y += reset.c
-verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+verstage-$(CONFIG_PICASSO_UART) += uart.c
verstage-y += tsc_freq.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
postcar-y += monotonic_timer.c
-postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
+postcar-$(CONFIG_PICASSO_UART) += uart.c
postcar-y += ramtop.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
postcar-y += tsc_freq.c
@@ -90,7 +90,7 @@ ramstage-y += smbus.c
ramstage-y += ramtop.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
-ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+ramstage-$(CONFIG_PICASSO_UART) += uart.c
ramstage-y += usb.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
@@ -117,7 +117,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi
# +-----------+
#
# EC ROM should be 64K aligned.
-STONEYRIDGE_FWM_POSITION=$(call int-add, \
+PICASSO_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
@@ -247,7 +247,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
$(OPT_SMUSCS_FILE) \
--combo-capable \
--flashsize $(CONFIG_ROM_SIZE) \
- --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \
+ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \
--output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
@@ -255,23 +255,23 @@ PHONY+=add_amdfw
INTERMEDIATE+=add_amdfw
# Calculate firmware position inside the ROM
-STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \
+PICASSO_FWM_ROM_POSITION=$(call int-add, \
$(call int-subtract, $(CONFIG_ROM_SIZE) \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000)
add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom
printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \
- "$(STONEYRIDGE_FWM_ROM_POSITION)"
+ "$(PICASSO_FWM_ROM_POSITION)"
dd if=$(obj)/amdfw.rom \
of=$(obj)/coreboot.pre conv=notrunc bs=1 \
- seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1
+ seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1
else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
-apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION)
+apu/amdfw-position := $(PICASSO_FWM_POSITION)
apu/amdfw-type := raw
endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index d1ea24ffd5..daeb7b60b4 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -75,7 +75,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE);
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
@@ -241,7 +241,7 @@ void generate_cpu_entries(struct device *device)
{
int cores, cpu;
- /* Stoney Ridge is single node, just report # of cores */
+ /* Picasso is single node, just report # of cores */
cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
cores++; /* number of cores is CmpCap+1 */
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 7221f955f6..19921e1c90 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -32,14 +32,14 @@
#include "chip.h"
/* Supplied by i2c.c */
-extern struct device_operations stoneyridge_i2c_mmio_ops;
+extern struct device_operations picasso_i2c_mmio_ops;
extern const char *i2c_acpi_name(const struct device *dev);
struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
- .init = stoney_init_cpus,
+ .init = picasso_init_cpus,
.acpi_fill_ssdt_generator = generate_cpu_entries,
};
@@ -132,7 +132,7 @@ static void enable_dev(struct device *dev)
sb_enable(dev);
else if (dev->path.type == DEVICE_PATH_MMIO)
if (i2c_acpi_name(dev) != NULL)
- dev->ops = &stoneyridge_i2c_mmio_ops;
+ dev->ops = &picasso_i2c_mmio_ops;
}
static void soc_init(void *chip_info)
@@ -147,8 +147,8 @@ static void soc_final(void *chip_info)
fam15_finalize(chip_info);
}
-struct chip_operations soc_amd_stoneyridge_ops = {
- CHIP_NAME("AMD StoneyRidge SOC")
+struct chip_operations soc_amd_picasso_ops = {
+ CHIP_NAME("AMD Picasso SOC")
.enable_dev = enable_dev,
.init = soc_init,
.final = soc_final
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 4f241e7b6b..ff9c845898 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -27,9 +27,9 @@
#define MAX_DRAM_CH 1
#define MAX_DIMMS_PER_CH 2
-#define STONEY_I2C_DEV_MAX 4
+#define PICASSO_I2C_DEV_MAX 4
-struct soc_amd_stoneyridge_config {
+struct soc_amd_picasso_config {
u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
enum {
DRAM_CONTENTS_KEEP,
@@ -59,7 +59,7 @@ struct soc_amd_stoneyridge_config {
* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
*/
u8 i2c_scl_reset;
- struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
+ struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX];
u8 stapm_percent;
u32 stapm_time_ms;
u32 stapm_power_mw;
@@ -74,7 +74,7 @@ struct soc_amd_stoneyridge_config {
u8 lvds_poseq_blon_to_varybl;
};
-typedef struct soc_amd_stoneyridge_config config_t;
+typedef struct soc_amd_picasso_config config_t;
extern struct device_operations pci_domain_ops;
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 1d9804d99c..fc9e9ecf06 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -105,7 +105,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = enable_smi_generation,
};
-void stoney_init_cpus(struct device *dev)
+void picasso_init_cpus(struct device *dev)
{
/* Clear for take-off */
if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index 7f65a4f3f3..9fe15886d9 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -46,7 +46,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus)
return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
}
-static const struct soc_amd_stoneyridge_config *get_soc_config(void)
+static const struct soc_amd_picasso_config *get_soc_config(void)
{
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
@@ -61,7 +61,7 @@ static const struct soc_amd_stoneyridge_config *get_soc_config(void)
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
{
- const struct soc_amd_stoneyridge_config *config;
+ const struct soc_amd_picasso_config *config;
if (bus >= ARRAY_SIZE(i2c_bus_address))
return NULL;
@@ -107,7 +107,7 @@ int dw_i2c_soc_dev_to_bus(struct device *dev)
static void dw_i2c_soc_init(bool is_early_init)
{
size_t i;
- const struct soc_amd_stoneyridge_config *config;
+ const struct soc_amd_picasso_config *config;
config = get_soc_config();
@@ -135,7 +135,7 @@ void i2c_soc_init(void)
dw_i2c_soc_init(false);
}
-struct device_operations stoneyridge_i2c_mmio_ops = {
+struct device_operations picasso_i2c_mmio_ops = {
/* TODO(teravest): Move I2C resource info here. */
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
@@ -188,7 +188,7 @@ static void restore_i2c_pin_registers(uint8_t gpio,
/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
void sb_reset_i2c_slaves(void)
{
- const struct soc_amd_stoneyridge_config *cfg;
+ const struct soc_amd_picasso_config *cfg;
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
struct soc_amd_i2c_save save_table[saved_pins_count];
uint8_t i, j, control;
diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h
index 71fe10eb26..f141a05714 100644
--- a/src/soc/amd/picasso/include/soc/acpi.h
+++ b/src/soc/amd/picasso/include/soc/acpi.h
@@ -20,7 +20,7 @@
#include <arch/acpi.h>
-#if CONFIG(STONEYRIDGE_LEGACY_FREE)
+#if CONFIG(PICASSO_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index d9d48ad27c..7d4764567a 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -29,7 +29,7 @@
#define SOC_EARLY_VMTRR_CAR_HEAP 2
#define SOC_EARLY_VMTRR_TEMPRAM 3
-void stoney_init_cpus(struct device *dev);
+void picasso_init_cpus(struct device *dev);
void check_mca(void);
#endif /* __PICASSO_CPU_H__ */
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index a63b16462b..7e2b7fc2f6 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -61,16 +61,16 @@
/* I/O Ranges */
#define ACPI_SMI_CTL_PORT 0xb2
-#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
-#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE
+#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
-#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
-#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x08) /* 6 bytes */
+#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
-#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index fa9206e33a..7ba179fbea 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -316,7 +316,7 @@
#define RST_CMD BIT(2)
#define SYS_RST BIT(1)
-struct stoneyridge_aoac {
+struct picasso_aoac {
int enable;
int status;
};
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 12ee2a8aca..5d1ed1877c 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -187,7 +187,7 @@ asmlinkage void car_stage_entry(void)
void SetMemParams(AMD_POST_PARAMS *PostParams)
{
- const struct soc_amd_stoneyridge_config *cfg;
+ const struct soc_amd_picasso_config *cfg;
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
if (!dev || !dev->chip_info) {
@@ -224,7 +224,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
{
- const struct soc_amd_stoneyridge_config *cfg;
+ const struct soc_amd_picasso_config *cfg;
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
struct _PLATFORM_CONFIGURATION *platform;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 45408ead02..711ebc592a 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -44,7 +44,7 @@
* waiting for each device to become available, a single delay will be
* executed.
*/
-const static struct stoneyridge_aoac aoac_devs[] = {
+const static struct picasso_aoac aoac_devs[] = {
{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
(FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) },
{ FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA },
@@ -56,22 +56,22 @@ const static struct stoneyridge_aoac aoac_devs[] = {
static int is_sata_config(void)
{
- return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE)
- || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE));
+ return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE)
+ || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE));
}
static inline int sb_sata_enable(void)
{
/* True if IDE or AHCI. */
- return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
- (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE);
+ return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
+ (SataAhci == CONFIG_PICASSO_SATA_MODE);
}
static inline int sb_ide_enable(void)
{
/* True if IDE or LEGACY IDE. */
- return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
- (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE);
+ return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
+ (SataLegacyIde == CONFIG_PICASSO_SATA_MODE);
}
void SetFchResetParams(FCH_RESET_INTERFACE *params)
@@ -91,11 +91,11 @@ void SetFchEnvParams(FCH_INTERFACE *params)
{
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
params->AzaliaController = AzEnable;
- params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
+ params->SataClass = CONFIG_PICASSO_SATA_MODE;
if (dev && dev->enabled) {
params->SataEnable = is_sata_config();
params->IdeEnable = !params->SataEnable;
- params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE ==
+ params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE ==
SataLegacyIde);
} else {
params->SataEnable = FALSE;
@@ -227,7 +227,7 @@ static void sb_lpc_decode(void)
| DECODE_ENABLE_ADLIB_PORT;
/* Decode SIOs at 2E/2F and 4E/4F */
- if (CONFIG(STONEYRIDGE_LEGACY_FREE))
+ if (CONFIG(PICASSO_LEGACY_FREE))
tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
lpc_enable_decode(tmp);