soc/amd/picasso: Remove all PSP runtime functions

Remove the mailbox call to notify the PSP that DRAM is ready.  This
is not supported on Family 17h.

Remove the selectable SMU firmware.  This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.

Clean up additional mentions of PSP within picasso.

Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

8 files changed, 0 insertions, 70 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index f691cb51a1..33aae2655f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_HDA
 	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_PI
-	select SOC_AMD_COMMON_BLOCK_PSP
 	select SOC_AMD_COMMON_BLOCK_CAR
 	select SOC_AMD_COMMON_BLOCK_S3
 	select C_ENVIRONMENT_BOOTBLOCK
@@ -65,7 +64,6 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_CONSOLE
 	select SSE2
 	select RTC
-	select SOC_AMD_PSP_SELECTABLE_SMU_FW
 
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index f6fa9fae90..93a8bbbbf2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -257,8 +257,6 @@ apu/amdfw-type := raw
 
 endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
 
-ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
-
 cbfs-files-y += smu_fw
 cbfs-files-y += smu_fw2
 smu_fw-file := $(SMUFWM_FILE)
@@ -266,6 +264,4 @@ smu_fw-type := raw
 smu_fw2-file := $(SMUFIRMWARE2_FILE)
 smu_fw2-type := raw
 
-endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y)
-
 endif # ($(CONFIG_SOC_AMD_PICASSO),y)
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 776f328c86..b9e98c538c 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -25,7 +25,6 @@
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
-#include <amdblocks/psp.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
 
@@ -157,10 +156,6 @@ static void earliest_ramstage(void *unused)
 	int s3_resume = acpi_s3_resume_allowed() &&
 			romstage_handoff_is_resume();
 	if (!s3_resume) {
-		post_code(0x46);
-		if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
-			psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
-
 		post_code(0x47);
 		do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
 	} else {
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index fc9e9ecf06..bee2b4b49f 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -121,23 +121,6 @@ static void model_15_init(struct device *dev)
 {
 	check_mca();
 	setup_lapic();
-
-	/*
-	 * Per AMD, sync an undocumented MSR with the PSP base address.
-	 * Experiments showed that if you write to the MSR after it has
-	 * been previously programmed, it causes a general protection fault.
-	 * Also, the MSR survives warm reset and S3 cycles, so we need to
-	 * test if it was previously written before writing to it.
-	 */
-	msr_t psp_msr;
-	uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
-	psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
-	psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	psp_msr = rdmsr(0xc00110a2);
-	if (psp_msr.lo == 0) {
-		psp_msr.lo = psp_bar;
-		wrmsr(0xc00110a2, psp_msr);
-	}
 }
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index ad76f3a83d..1d89fd7ec0 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -18,7 +18,6 @@
 #define __SOC_PICASSO_IOMAP_H__
 
 /* MMIO Ranges */
-#define PSP_MAILBOX_BAR3_BASE		0xf0a00000
 #define SPI_BASE_ADDRESS		0xfec10000
 #define IO_APIC2_ADDR			0xfec20000
 
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index 8a885f2c0b..d6887f9b38 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -95,13 +95,6 @@
 #define PCIE4_DEVFN		PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
 #define SOC_PCIE4_DEV		_SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
 
-/* Platform Security Processor */
-#define PSP_DEV			0x8
-#define PSP_FUNC		0
-#define PSP_DEVID		0x1578
-#define PSP_DEVFN		PCI_DEVFN(PSP_DEV, PSP_FUNC)
-#define SOC_PSP_DEV		_SOC_DEV(PSP_DEV, PSP_FUNC)
-
 /* HD Audio 1 */
 #define HDA1_DEV		0x9
 #define HDA1_FUNC		2
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 0f72a68567..b28522e60f 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -277,11 +277,6 @@
 #define SPI100_HOST_PREF_CONFIG		0x2c
 #define   SPI_RD4DW_EN_HOST		BIT(15)
 
-/* Platform Security Processor D8F0 */
-#define PSP_MAILBOX_BAR			PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
-#define PSP_BAR_ENABLES			0x48
-#define  PSP_MAILBOX_BAR_EN		0x10
-
 /* IO 0xcf9 - Reset control port*/
 #define   FULL_RST			BIT(3)
 #define   RST_CMD			BIT(2)
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 5d1ed1877c..904f556202 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -32,7 +32,6 @@
 #include <soc/northbridge.h>
 #include <soc/romstage.h>
 #include <soc/southbridge.h>
-#include <amdblocks/psp.h>
 
 #include "chip.h"
 
@@ -41,28 +40,6 @@ void __weak mainboard_romstage_entry(int s3_resume)
 	/* By default, don't do anything */
 }
 
-static void load_smu_fw1(void)
-{
-	u32 base, limit, cmd;
-
-	/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
-	base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
-	limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
-	pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
-	pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
-
-	/* Preload a value into "BAR3" and enable it */
-	pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
-	pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
-
-	/* Enable memory access and master */
-	cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
-	cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-	pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
-
-	psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
-}
-
 static void agesa_call(void)
 {
 	post_code(0x37);
@@ -94,9 +71,6 @@ asmlinkage void car_stage_entry(void)
 
 	console_init();
 
-	if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
-		load_smu_fw1();
-
 	mainboard_romstage_entry(s3_resume);
 
 	bsp_agesa_call();
@@ -143,9 +117,6 @@ asmlinkage void car_stage_entry(void)
 		post_code(0x61);
 	}
 
-	post_code(0x42);
-	psp_notify_dram();
-
 	post_code(0x43);
 	if (cbmem_recovery(s3_resume))
 		printk(BIOS_CRIT, "Failed to recover cbmem\n");