diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-11 12:34:04 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:41:04 +0000 |
commit | 19ea0169108dc2eff743ae640a8108eb5852612d (patch) | |
tree | 90a9e0463572f14ae900b631495e7d55c26d61da /src/soc/amd/picasso | |
parent | 7e5a2660bc927adac1fc420f94c111b8f8aae191 (diff) | |
download | coreboot-19ea0169108dc2eff743ae640a8108eb5852612d.tar.xz |
soc/amd/picasso: Remove most stoneyridge USB
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r-- | src/soc/amd/picasso/Kconfig | 21 | ||||
-rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 6 | ||||
-rw-r--r-- | src/soc/amd/picasso/acpi/globalnvs.asl | 11 | ||||
-rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 41 | ||||
-rw-r--r-- | src/soc/amd/picasso/acpi/usb.asl | 325 | ||||
-rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 1 | ||||
-rw-r--r-- | src/soc/amd/picasso/include/soc/nvs.h | 7 | ||||
-rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 40 | ||||
-rw-r--r-- | src/soc/amd/picasso/southbridge.c | 22 | ||||
-rw-r--r-- | src/soc/amd/picasso/usb.c | 12 |
10 files changed, 9 insertions, 477 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9317119c99..f692f95884 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -151,27 +151,6 @@ config EHCI_BAR hex default 0xfef00000 -config STONEYRIDGE_XHCI_ENABLE - bool "Enable Stoney Ridge XHCI Controller" - default y - help - The XHCI controller must be enabled and the XHCI firmware - must be added in order to have USB 3.0 support configured - by coreboot. The OS will be responsible for enabling the XHCI - controller if the XHCI firmware is available but the - XHCI controller is not enabled by coreboot. - -config STONEYRIDGE_XHCI_FWM - bool "Add xhci firmware" - default y - help - Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 - -config STONEYRIDGE_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" - depends on STONEYRIDGE_XHCI_FWM - config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9aedbd1445..dbb0e8e4fd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -175,8 +175,6 @@ endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) - OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) @@ -196,8 +194,7 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBP OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ @@ -215,7 +212,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index e780a642c6..cdb32cc0d3 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,19 +58,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 2, - EHCE, 1, // EHCI, 18 - , 4, - XHCE, 1, // XCHI, 23 + , 8, SD_E, 1, // SD, 24 , 2, ESPI, 1, // ESPI, 27 - , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3623814080..8cdb4d2750 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -208,27 +208,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { U2RP, 1, /* Usb2 Ref Clock Powerdown */ U3RP, 1, /* Usb3 Ref Clock Powerdown */ - /* XHCI_PM registers */ - offset (0x1c00), - , 1, - ,6, - U3PY, 1, - , 7, - UD3P, 1, /* bit 15 */ - U3PR, 1, /* bit 16 */ - , 11, - FWLM, 1, /* FirmWare Load Mode */ - FPLS, 1, /* Fw PreLoad Start */ - FPLC, 1, /* Fw PreLoad Complete */ - - offset (0x1c04), - UA04, 16, - , 15, - ROAM, 1, /* 1= ROM 0=RAM */ - - offset (0x1c08), - UA08, 32, - /* AOAC Registers */ offset (0x1e4a), /* I2C0 D3 Control */ I0TD, 2, @@ -442,8 +421,6 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(18) { U2D0()} /* EHCI */ - Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ Store(0x00, SDTD) Store(One, SDPD) @@ -505,8 +482,6 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(18) { U2D3()} /* EHCI */ - Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ Store(Zero, SDPD) Store(SDDS, Local0) @@ -541,26 +516,10 @@ Method(FDDC, 2, Serialized) Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { - FDDC(23, 3) - } - } - if(LNotEqual(U2TD, 0x03)) { - FDDC(18, 3) - } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { - FDDC(23, 0) - } - } - if(LEqual(U2TD, 0x03)) { - FDDC(18, 0) - } if(LEqual(\UT0E, zero)) { if(LNotEqual(U0TD, 0x03)) { FDDC(11, 3) diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index f2ee8f6427..2af0c1a794 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -30,9 +30,6 @@ Device(EHC0) { Device (HS08) { Name (_ADR, 8) } } - Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -55,9 +52,6 @@ Device(XHC0) { Device (SS02) { Name (_ADR, 2) } Device (SS03) { Name (_ADR, 3) } - Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -71,322 +65,3 @@ Device(XHC0) { } } /* end XHC0 */ - -Scope(\_SB) -{ - Name(XHD0, 0) - Name(XHD3, 0) - PowerResource(P0U3, 0, 0) { - Method(_STA) { - Return(XHD0) - } - Method(_ON) { - Store(0x01, XHD0) - } - Method(_OFF) { - Store(0x00, XHD0) - } - } - PowerResource(P3U3, 0, 0) { - Method(_STA) { - Return(XHD3) - } - Method(_ON) { - Store(0x01, XHD3) - } - Method(_OFF) { - Store(0x00, XHD3) - } - } - - Name(EHD0, 0) - Name(EHD3, 0) - PowerResource(P0U2, 0, 0) { - Method(_STA) { - Return(EHD0) - } - Method(_ON) { - Store(0x01, EHD0) - } - Method(_OFF) { - Store(0x00, EHD0) - } - } - PowerResource(P3U2, 0, 0) { - Method(_STA) { - Return(EHD3) - } - Method(_ON) { - Store(0x01, EHD3) - } - Method(_OFF) { - Store(0x00, EHD3) - } - } -} - -OperationRegion(EHMC, SystemMemory, EH10, 0x100) -Field(EHMC, DwordAcc, NoLock, Preserve) -{ - Offset(0xb0), - , 5, - ESIM, 1, -} - -Method(U2D3,0, Serialized) -{ - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (ESIM, SSIM) - } - - if (LEqual(E_PS, 3)) { - Store (Zero, RQTY) - Store (One, RQ18) - - Store (U2SR, Local0) - while (Local0) { - Store (U2SR, Local0) - } - - Store (Zero, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0, Zero)) { - Store (U2DS, Local0) - } - - Store (0x03,U2TD) - - if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ - PWGC (0x40, 0) - Store (One, U2RP) - } - } -} - -Method(U2D0,0, Serialized) -{ - PWGC (0x40, 1) - Store (Zero, U2RP) - Store (0x00,U2TD) - - Store (Zero, U2TD) - Store (One, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0,0x7)) { - Store (U2DS, Local0) - } - - Store (One, RQTY) - Store (One, RQ18) - Store (U2SR, Local0) - while (LNot(Local0)) { - Store (U2SR, Local0) - } - Store (EHID, EH2C) - - - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (SSIM, ESIM) - } - - Store (ES54, EH54) - Store (ES64, EH64) -} - -Method(LXFW,3, Serialized) //Load Xhci FirmWare -{ - Store (One, FWLM) /* Firmware Load Mode */ - Store (Arg0, ROAM) /* ROM/RAM */ - Store (Arg1, UA04) - Store (Arg2, UA08) - Store (One, FPLS) /* Firmware Preload Start */ - Store (FPLC, Local0) /* Firmware Preload Complete */ - while (LNot(Local0)) { - Store (FPLC, Local0) - } - Store (Zero, FPLS) -} - -Method(U3D3,0, Serialized) -{ - if (LEqual(U_PS, 3)) { - X0_S () - - Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ - And (PGA3, 0x20, Local0) - while (LNot(Local0)) { /* wait for it to complete */ - And (PGA3, 0x20, Local0) - } - Store (One, UD3P) /* U3P_D3Cold_PWRDN */ - - Store (Zero, U3PD) /* PwrOnDev */ - Store (U3DS, Local0) - while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ - Store (U3DS, Local0) - } - - Store (0x3, U3TD) /* TargetedDeviceState */ - - Store (One, U3RP) /* USB3_RefClk_Pwdn */ - - if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ - And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ - Store (One, U2RP) /* USB2_RefClk_Pwdn */ - } - Store (Zero, U3PG) /* XhcPwrGood */ - Store (One, U3PS) /* Usb3PowerSel */ - } -} - -Method(U3D0,0, Serialized) -{ - Store (Zero, U3PS) /* Usb3PowerSel */ - Store (One, U3PG) /* XhcPwrGood */ - - Store (Zero, U2RP) - Store (Zero, U3RP) - - And (PGA3, 0xdf, Local0) - Or (Local0, 0x40, Local0) - Store (Local0, PGA3) /* SwUsb2S5RstB */ - - Store (Zero, U3TD) /* TargetedDeviceState */ - Store (One, U3PD) /* PwrOnDev */ - - Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ - while (LNot(Lequal(Local0, 0x7))) { - Store (U3DS, Local0) - } - - Store (U3PY, Local0) /* USB3 PHY Lock */ - while (LNot(Local0)) { - Store (U3PY, Local0) - } - - Store (Zero, U3PR) /* U3P_RESTORE_RESET */ - - Store (AUSS, Local0) /* AutoSizeStart */ - if (LNotEqual(Local0,1)) { - Store(One, AUSS) - } - Store (AUSS, Local0) - while (LNotEqual(Local0,1)) { - Store (AUSS, Local0) - } - - LXFW (1, FW00, FW01) - LXFW (0, FW02, FW03) - - X0_R () - - Store (One, U3PR) /* U3P_RESTORE_RESET */ - Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ - Store (One, U3TD) /* TargetedDeviceState */ -} - -Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ -CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */ -CreateDWordField(SVBF, 0x004, S004) -CreateDWordField(SVBF, 0x008, S008) -CreateDWordField(SVBF, 0x00C, S00C) -CreateDWordField(SVBF, 0x018, S018) -CreateDWordField(SVBF, 0x01C, S01C) -CreateDWordField(SVBF, 0x020, S020) -CreateDWordField(SVBF, 0x030, S030) -CreateDWordField(SVBF, 0x118, S118) -CreateDWordField(SVBF, 0x158, S158) -CreateDWordField(SVBF, 0x198, S198) -CreateDWordField(SVBF, 0x1D8, S1D8) -CreateDWordField(SVBF, 0x300, S300) -CreateDWordField(SVBF, 0x304, S304) -CreateDWordField(SVBF, 0x308, S308) -CreateDWordField(SVBF, 0x30C, S30C) -CreateDWordField(SVBF, 0x310, S310) -CreateDWordField(SVBF, 0x428, S428) -CreateDWordField(SVBF, 0x438, S438) -CreateDWordField(SVBF, 0x43C, S43C) -CreateDWordField(SVBF, 0x458, S458) -CreateDWordField(SVBF, 0x468, S468) -CreateDWordField(SVBF, 0x46C, S46C) -CreateDWordField(SVBF, 0x470, S470) -CreateDWordField(SVBF, 0x480, S480) -CreateDWordField(SVBF, 0x484, S484) -CreateDWordField(SVBF, 0x488, S488) -CreateDWordField(SVBF, 0x48C, S48C) -CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */ -CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */ -CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */ -CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */ -CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */ - -Method(X0_S,0) -{ - Store (XH2C, XHID) - Store (0x00000000, IDEX) Store (DATA, S000) - Store (0x00000004, IDEX) Store (DATA, S004) - Store (0x00000008, IDEX) Store (DATA, S008) - Store (0x0000000c, IDEX) Store (DATA, S00C) - Store (0x00000018, IDEX) Store (DATA, S018) - Store (0x0000001c, IDEX) Store (DATA, S01C) - Store (0x00000020, IDEX) Store (DATA, S020) - Store (0x00000030, IDEX) Store (DATA, S030) - Store (0x00000118, IDEX) Store (DATA, S118) - Store (0x00000158, IDEX) Store (DATA, S158) - Store (0x00000198, IDEX) Store (DATA, S198) - Store (0x000001d8, IDEX) Store (DATA, S1D8) - Store (0x00000300, IDEX) Store (DATA, S300) - Store (0x00000304, IDEX) Store (DATA, S304) - Store (0x00000308, IDEX) Store (DATA, S308) - Store (0x0000030c, IDEX) Store (DATA, S30C) - Store (0x00000310, IDEX) Store (DATA, S310) - Store (0x40000028, IDEX) Store (DATA, S428) - Store (0x40000038, IDEX) Store (DATA, S438) - Store (0x4000003c, IDEX) Store (DATA, S43C) - Store (0x40000058, IDEX) Store (DATA, S458) - Store (0x40000068, IDEX) Store (DATA, S468) - Store (0x4000006c, IDEX) Store (DATA, S46C) - Store (0x40000070, IDEX) Store (DATA, S470) - Store (0x40000080, IDEX) Store (DATA, S480) - Store (0x40000084, IDEX) Store (DATA, S484) - Store (0x40000088, IDEX) Store (DATA, S488) - Store (0x4000008c, IDEX) Store (DATA, S48C) -} - -Method(X0_R,0) -{ - Store (XHID, XH2C) - Store (0x00000000, IDEX) Store (S000, DATA) - Store (0x00000004, IDEX) Store (S004, DATA) - Store (0x00000008, IDEX) Store (S008, DATA) - Store (0x0000000c, IDEX) Store (S00C, DATA) - Store (0x00000018, IDEX) Store (S018, DATA) - Store (0x0000001c, IDEX) Store (S01C, DATA) - Store (0x00000020, IDEX) Store (S020, DATA) - Store (0x00000030, IDEX) Store (S030, DATA) - Store (0x00000118, IDEX) Store (S118, DATA) - Store (0x00000158, IDEX) Store (S158, DATA) - Store (0x00000198, IDEX) Store (S198, DATA) - Store (0x000001d8, IDEX) Store (S1D8, DATA) - Store (0x00000300, IDEX) Store (S300, DATA) - Store (0x00000304, IDEX) Store (S304, DATA) - Store (0x00000308, IDEX) Store (S308, DATA) - Store (0x0000030c, IDEX) Store (S30C, DATA) - Store (0x00000310, IDEX) Store (S310, DATA) - Store (0x40000028, IDEX) Store (S428, DATA) - Store (0x40000038, IDEX) Store (S438, DATA) - Store (0x4000003c, IDEX) Store (S43C, DATA) - Store (0x40000058, IDEX) Store (S458, DATA) - Store (0x40000068, IDEX) Store (S468, DATA) - Store (0x4000006c, IDEX) Store (S46C, DATA) - Store (0x40000070, IDEX) Store (S470, DATA) - Store (0x40000080, IDEX) Store (S480, DATA) - Store (0x40000084, IDEX) Store (S484, DATA) - Store (0x40000088, IDEX) Store (S488, DATA) - Store (0x4000008c, IDEX) Store (S48C, DATA) -} diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 7e2b7fc2f6..ad76f3a83d 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -39,7 +39,6 @@ #define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ #define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ #define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ #define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 5023df6b27..1c02bb7e87 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -52,12 +52,7 @@ typedef struct global_nvs_t { uint8_t tmax; /* 0x30 - CPU Tj_max */ uint8_t pad1[3]; aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t unused[200]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 7ba179fbea..a5892bbd87 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -178,31 +178,6 @@ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ -/* XHCI_PM Registers: 0xfed81c00 */ -#define XHCI_PM_INDIRECT_INDEX 0x48 -#define XHCI_PM_INDIRECT_DATA 0x4c -#define XHCI_OVER_CURRENT_CONTROL 0x30 -#define USB_OC0 0 -#define USB_OC1 1 -#define USB_OC2 2 -#define USB_OC3 3 -#define USB_OC4 4 -#define USB_OC5 5 -#define USB_OC6 6 -#define USB_OC7 7 -#define USB_OC_DISABLE 0xf -#define USB_OC_DISABLE_ALL 0xffff -#define OC_PORT0_SHIFT 0 -#define OC_PORT1_SHIFT 4 -#define OC_PORT2_SHIFT 8 -#define OC_PORT3_SHIFT 12 - -#define EHCI_OVER_CURRENT_CONTROL 0x70 -#define EHCI_HUB_CONFIG4 0x90 -#define DEBUG_PORT_SELECT_SHIFT 16 -#define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) - /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 #define FCH_AOAC_D3_CONTROL_I2C0 0x4a @@ -212,8 +187,6 @@ #define FCH_AOAC_D3_CONTROL_UART0 0x56 #define FCH_AOAC_D3_CONTROL_UART1 0x58 #define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -231,8 +204,6 @@ #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -332,10 +303,7 @@ typedef struct aoac_devs { unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; unsigned int st_e:1; /* 15: SATA */ - unsigned int :2; - unsigned int ehce:1; /* 18: EHCI */ - unsigned int :4; - unsigned int xhce:1; /* 23: xHCI */ + unsigned int :8; unsigned int sd_e:1; /* 24: SDIO */ unsigned int :2; unsigned int espi:1; /* 27: ESPI */ @@ -350,11 +318,6 @@ struct soc_power_reg { uint16_t wake_from; }; -#define XHCI_FW_SIG_OFFSET 0xc -#define XHCI_FW_ADDR_OFFSET 0x6 -#define XHCI_FW_SIZE_OFFSET 0x8 -#define XHCI_FW_BOOTRAM_SIZE 0x8000 - void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); @@ -403,6 +366,7 @@ uint64_t get_uma_base(void); * a default weak function in usb.c if the mainboard doesn't have any * over current support. */ +#define USB_OC_DISABLE_ALL 0xffff int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 711ebc592a..dca3591f85 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -77,7 +77,6 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -579,10 +578,6 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); @@ -595,29 +590,12 @@ static void set_sb_final_nvs(void) gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } void southbridge_final(void *chip_info) diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 00f82375e8..ae6c476055 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -29,17 +29,13 @@ static void set_usb_over_current(struct device *dev) uint16_t map = USB_OC_DISABLE_ALL; if (dev->path.pci.devfn == XHCI_DEVFN) { - if (mainboard_get_xhci_oc_map(&map) == 0) { - xhci_pm_write32(XHCI_PM_INDIRECT_INDEX, - XHCI_OVER_CURRENT_CONTROL); - xhci_pm_write16(XHCI_PM_INDIRECT_DATA, map); - } + if (mainboard_get_xhci_oc_map(&map) == 0) + ; // TODO } - if (dev->path.pci.devfn == EHCI1_DEVFN) { + if (dev->path.pci.devfn == EHCI1_DEVFN) if (mainboard_get_ehci_oc_map(&map) == 0) - pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map); - } + ; // TODO } int __weak mainboard_get_xhci_oc_map(uint16_t *map) |