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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-12-01 18:14:39 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-04 12:24:25 +0000
commitf65c1e40885377a07794fc59f38fce1c9230854f (patch)
tree610e56fc65eac6d5cab5c0581b0710415a51804c /src/soc/amd/picasso
parent73a544d4533fa8305f1c0a809137b5e2151ea17e (diff)
downloadcoreboot-f65c1e40885377a07794fc59f38fce1c9230854f.tar.xz
amdblocks/acpimmio: Unify BIOSRAM usage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h32
-rw-r--r--src/soc/amd/picasso/memmap.c10
-rw-r--r--src/soc/amd/picasso/northbridge.c2
-rw-r--r--src/soc/amd/picasso/southbridge.c24
4 files changed, 1 insertions, 67 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 0fb187dc52..cbf95b9b16 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -335,38 +335,6 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void fch_pre_init(void);
void fch_early_init(void);
void set_uart_config(int idx);
-/**
- * @brief Save the UMA bize
- *
- * @param size = in bytes
- *
- * @return none
- */
-void save_uma_size(uint32_t size);
-/**
- * @brief Save the UMA base address
- *
- * @param base = 64bit base address
- *
- * @return none
- */
-void save_uma_base(uint64_t base);
-/**
- * @brief Get the saved UMA size
- *
- * @param none
- *
- * @return size in bytes
- */
-uint32_t get_uma_size(void);
-/**
- * @brief Get the saved UMA base
- *
- * @param none
- *
- * @return 64bit base address
- */
-uint64_t get_uma_base(void);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 82d6fb6e8e..ae5a331259 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -28,16 +28,6 @@
#include <soc/iomap.h>
#include <amdblocks/acpimmio.h>
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
- biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- return biosram_read32(BIOSRAM_CBMEM_TOP);
-}
-
#if CONFIG(ACPI_BERT)
#if CONFIG_SMM_TSEG_SIZE == 0x0
#define BERT_REGION_MAX_SIZE 0x100000
diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c
index 08807f3321..4a1493cba3 100644
--- a/src/soc/amd/picasso/northbridge.c
+++ b/src/soc/amd/picasso/northbridge.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/biosram.h>
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
@@ -29,7 +30,6 @@
#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
-#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <soc/iomap.h>
#include <stdint.h>
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 041d262af7..0dff4bcae3 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -501,27 +501,3 @@ static void set_pci_irqs(void *unused)
* on entry into BS_DEV_ENABLE.
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-void save_uma_size(uint32_t size)
-{
- biosram_write32(BIOSRAM_UMA_SIZE, size);
-}
-
-void save_uma_base(uint64_t base)
-{
- biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
- biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
-}
-
-uint32_t get_uma_size(void)
-{
- return biosram_read32(BIOSRAM_UMA_SIZE);
-}
-
-uint64_t get_uma_base(void)
-{
- uint64_t base;
- base = biosram_read32(BIOSRAM_UMA_BASE);
- base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
- return base;
-}