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| author | Aaron Durbin <adurbin@chromium.org> | 2020-04-11 11:58:57 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-05 12:59:43 +0000 |
| commit | 1d0b99ba1df910677b3ac238a16b88bcec2d49f8 (patch) | |
| tree | 94ad3d1ce23a47f655a2f5cac32eebc64b4e1482 /src/soc/amd/picasso | |
| parent | 314c716aff9895221f1f5b8bef4d3889a7749c0a (diff) | |
| download | coreboot-1d0b99ba1df910677b3ac238a16b88bcec2d49f8.tar.xz | |
soc/amd/picasso: add Kconfig option to disable rom sharing
Add a knob for mainboards to request disablement of the SPI
flash ROM sharing in the chipset. The chipset allows the board
to share the SPI flash bus and needs a pin to perform the request.
If the board design does not employ SPI flash ROM sharing then it's
imperative to ensure this option is selected, especially if the
pin is being utilized by something else in the board design.
BUG=b:153502861
Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3d699667fe..a42629bdff 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -216,6 +217,14 @@ config PICASSO_LPC_IOMUX Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required. +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0d54294543..d742038183 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -360,6 +360,9 @@ void fch_early_init(void) { sb_print_pmxc0_status(); i2c_soc_early_init(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); } void sb_enable(struct device *dev) |