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| author | Marc Jones <marcj303@gmail.com> | 2017-05-07 16:47:36 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:03 +0000 |
| commit | 21cde8b83227fa324f246672b1e2d58408ea6bf8 (patch) | |
| tree | b5c0ce8fd9426def5d0e8863265840c891fb1076 /src/soc/amd/stoneyridge/Kconfig | |
| parent | 244848462def7075e0c812a2f71c408668cacfe4 (diff) | |
| download | coreboot-21cde8b83227fa324f246672b1e2d58408ea6bf8.tar.xz | |
soc/amd/stoneyridge: Add CPU files
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/Kconfig')
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 53 |
1 files changed, 50 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 4cd3116ecd..591037f4ab 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -13,14 +13,61 @@ ## GNU General Public License for more details. ## -config SOC_AMD_STONEYRIDGE +config SOC_AMD_STONEYRIDGE_FP4 bool + help + AMD Stoney Ridge FP4 support + +config SOC_AMD_STONEYRIDGE_FT4 + bool + help + AMD Stoney Ridge FT4 support + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET + select LAPIC_MONOTONIC_TIMER select SOC_AMD_COMMON + select SOC_AMD_PI + select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in PI vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. -if SOC_AMD_STONEYRIDGE +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config CPU_ADDR_BITS + int + default 48 + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -164,4 +211,4 @@ config STONEYRIDGE_UART to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. -endif # SOC_AMD_STONEYRIDGE +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 |