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| author | Marc Jones <marc.jones@scarletltd.com> | 2017-06-18 17:33:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-31 17:29:35 +0000 |
| commit | 257db58bdb06994e6082afff047e1a3d2ad8fe9a (patch) | |
| tree | d620d4ec0fa210c2b49a4bf076e6e3a3bb73cb9f /src/soc/amd/stoneyridge/Makefile.inc | |
| parent | 583806a79d36a2aff5cb6069150ebe173130b00e (diff) | |
| download | coreboot-257db58bdb06994e6082afff047e1a3d2ad8fe9a.tar.xz | |
soc/amd/stoneyridge: Add GNVS
Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/Makefile.inc')
| -rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 416d4bdacf..f3c2b1b5d9 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -61,7 +61,7 @@ verstage-y += tsc_freq.c ramstage-y += chip.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += fixme.c ramstage-y += gpio.c ramstage-y += hda.c |