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authorPatrick Georgi <pgeorgi@google.com>2018-10-23 14:35:37 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-11-28 13:13:04 +0000
commit4fbefc5282916550fe7cdd718263fe4cd957a2f3 (patch)
tree401eda723d8c16a545d83c83df4f0e8a6c05cae4 /src/soc/amd/stoneyridge/acpi.c
parent37d5f004ab5751d2521200df08ef86ce1c3fed47 (diff)
downloadcoreboot-4fbefc5282916550fe7cdd718263fe4cd957a2f3.tar.xz
soc/amd/stoneyridge: Replace public magic numbers
Some "magic" numbers became public available registers/bits after the code was originally written. Find all magic numbers, and if available in a public BKDG than replace them with literals. BUG=b:117648026 TEST=Build and boot grunt. Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi.c')
-rw-r--r--src/soc/amd/stoneyridge/acpi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index d56e105607..1f6e62abb7 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -31,6 +31,7 @@
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
+#include <soc/northbridge.h>
#include <soc/nvs.h>
#include <soc/gpio.h>
@@ -237,11 +238,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
void generate_cpu_entries(struct device *device)
{
int cores, cpu;
- struct device *cdb_dev;
/* Stoney Ridge is single node, just report # of cores */
- cdb_dev = dev_find_slot(0, NB_DEVFN);
- cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
+ cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
+ cores++; /* number of cores is CmpCap+1 */
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);