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| author | Marc Jones <marcj303@gmail.com> | 2017-08-06 17:42:35 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-14 19:36:50 +0000 |
| commit | 6bfcf666b08fcfd3f163674fcc37f4bbd9b62a30 (patch) | |
| tree | d7ff0ae3a1dd42c0e1835bc9dc13021b2f39bfb6 /src/soc/amd/stoneyridge/acpi.c | |
| parent | 029dfff30cc468b3e21c2004a135d3380a8c20e6 (diff) | |
| download | coreboot-6bfcf666b08fcfd3f163674fcc37f4bbd9b62a30.tar.xz | |
stoneyridge: Fix CPU ASL \_PR table
The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 9ebe8dea7e..9788a91153 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,6 +26,7 @@ #include <arch/ioapic.h> #include <cbmem.h> #include <device/device.h> +#include <device/pci.h> #include <soc/acpi.h> #include <soc/southbridge.h> #include <soc/nvs.h> @@ -231,6 +232,32 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } +void generate_cpu_entries(device_t device) +{ + int cores, cpu, plen = 6; + u32 pcontrol_blk = ACPI_GPE0_BLK; + device_t cdb_dev; + + /* Stoney Ridge is single node, just report # of cores */ + cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); + cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1; + + printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); + + + /* Generate BSP \_PR.CPU0 */ + acpigen_write_processor(0, pcontrol_blk, plen); + acpigen_pop_len(); + + /* Generate AP \_PR.CPUx */ + pcontrol_blk = 0; + plen = 0; + for (cpu = 1; cpu < cores; cpu++) { + acpigen_write_processor(cpu, pcontrol_blk, 0); + acpigen_pop_len(); + } +} + unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) |