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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-27 08:23:15 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:30:45 +0000 |
| commit | fc458cdc5374a293483455acdd42cdbdd032ae27 (patch) | |
| tree | 41659c036bc61e28137ce574c99eb2bf2c675441 /src/soc/amd/stoneyridge/acpi/globalnvs.asl | |
| parent | 87471366e42106b136d6cd0fba008b8c7eb53f85 (diff) | |
| download | coreboot-fc458cdc5374a293483455acdd42cdbdd032ae27.tar.xz | |
amd/stoneyridge: Create gnvs entries for AOAC devices
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index ba50e3874d..810c97b9e4 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -47,6 +47,25 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TCRT, 8, // 0x2E - Critical Threshold TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max + Offset (0x34), // 0x34 - AOAC Device Enables + , 5, + IC0E, 1, // I2C0, 5 + IC1E, 1, // I2C1, 6 + IC2E, 1, // I2C2, 7 + IC3E, 1, // I2C3, 8 + , 2, + UT0E, 1, // UART0, 11 + UT1E, 1, // UART1, 12 + , 2, + ST_E, 1, // SATA, 15 + , 2, + EHCE, 1, // EHCI, 18 + , 4, + XHCE, 1, // XCHI, 23 + SD_E, 1, // SD, 24 + , 2, + ESPI, 1, // ESPI, 27 + , 4, /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> |