diff options
author | Marc Jones <marc.jones@scarletltd.com> | 2017-06-18 17:33:30 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-07-31 17:29:35 +0000 |
commit | 257db58bdb06994e6082afff047e1a3d2ad8fe9a (patch) | |
tree | d620d4ec0fa210c2b49a4bf076e6e3a3bb73cb9f /src/soc/amd/stoneyridge/acpi/lpc.asl | |
parent | 583806a79d36a2aff5cb6069150ebe173130b00e (diff) | |
download | coreboot-257db58bdb06994e6082afff047e1a3d2ad8fe9a.tar.xz |
soc/amd/stoneyridge: Add GNVS
Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/lpc.asl')
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/lpc.asl | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index 783a2c952c..a41357a306 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -14,8 +14,9 @@ */ /* 0:14.3 - LPC */ -Device(LIBR) { +Device(LPCB) { Name(_ADR, 0x00140003) + /* Method(_INI) { * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") } */ /* End Method(_SB.SBRDG._INI) */ @@ -37,7 +38,7 @@ Device(LIBR) { ) }) - Method(_CRS,0,NotSerialized) + Method(_CRS,0,Serialized) { CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length @@ -100,4 +101,4 @@ Device(LIBR) { IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -} /* end LIBR */ +} /* end LPCB */ |