diff options
author | Marc Jones <marcj303@gmail.com> | 2017-05-15 18:55:11 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:18 +0000 |
commit | 1587dc8a2b4ddfe110cd0239c6506a320cccac96 (patch) | |
tree | ab9b3b3ae63461e9fa8caf4c3fe4410f78f664c3 /src/soc/amd/stoneyridge/acpi | |
parent | 21cde8b83227fa324f246672b1e2d58408ea6bf8 (diff) | |
download | coreboot-1587dc8a2b4ddfe110cd0239c6506a320cccac96.tar.xz |
soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/northbridge.asl | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl new file mode 100644 index 0000000000..c5876ff4d4 --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PMOD) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +Device(AZHD) { /* 0:9.2 - HD Audio */ + Name(_ADR, 0x00090002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method (_INI, 0, NotSerialized) + { + If (LEqual (OSVR, 0x03)) + { + Store (Zero, NSEN) + Store (One, NSDO) + Store (One, NSDI) + } + } +} /* end AZHD */ |