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| author | Caveh Jalali <caveh@chromium.org> | 2019-05-13 20:55:06 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-05-14 23:33:54 +0000 |
| commit | cd51d7ced5a4996253c6dfc816ab7ef82533b2da (patch) | |
| tree | 0fb14d2186d4062a1ecc12cd26c5cf8ef3eea5d4 /src/soc/amd/stoneyridge/acpi | |
| parent | d1ad37847da61d243f691590005865df505dc31f (diff) | |
| download | coreboot-cd51d7ced5a4996253c6dfc816ab7ef82533b2da.tar.xz | |
mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips
This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133
chips.
BUG=b:132206809
TEST=boots on atlas with C-die and D-die memory chips
localhost ~ # mosys memory spd print all
0 | LPDDR3 | SO-DIMM
1 | LPDDR3 | SO-DIMM
0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG
1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG
0 | 8192 | 2 | 64
1 | 8192 | 2 | 64
0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133
1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133
localhost ~ #
Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
0 files changed, 0 insertions, 0 deletions