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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-10 16:08:37 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-13 17:21:56 +0000 |
| commit | 3e4e4c5f88dbb65e789410048bcb83fcdb30c989 (patch) | |
| tree | d7c1dad9977cd01f745f5dc77551618c07381014 /src/soc/amd/stoneyridge/acpi | |
| parent | c4f9f4bdae57a62ef14a526e51ce2b7d894a0682 (diff) | |
| download | coreboot-3e4e4c5f88dbb65e789410048bcb83fcdb30c989.tar.xz | |
soc/amd/stoneyridge: Fix DRAM clear check
Explicitly add #include files to romstage.c to ensure sizes of the
devicetree structures are correct. The AMD support headers have an
open #pragma pack(1) which causes structure sizes to change based on
include ordering in different compilation units. More concretely, this
fixes a bug where dev->chip_info is incorrectly detected as 0.
Also shorten a printk string to bring the source line within 80 columns.
Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
0 files changed, 0 insertions, 0 deletions